| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系在職專班 | zh_TW |
| DC.creator | 何紹仰 | zh_TW |
| DC.creator | Shao-Yang Ho | en_US |
| dc.date.accessioned | 2019-7-10T07:39:07Z | |
| dc.date.available | 2019-7-10T07:39:07Z | |
| dc.date.issued | 2019 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=105553023 | |
| dc.contributor.department | 通訊工程學系在職專班 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 對半導體產業來說高效能及節能這個議題至今產學界仍不斷地找尋最佳的方案，本質來說數位積體電路，若能降低其本身功耗並最大化其效能可大幅增加產品競爭力。
當今半導體先進製程中標準元件庫提供了不同高度的選擇， 大高度元件(12T)提供更高的驅動力，代價是更大的面積和功耗。低高度元件(7T)具有較小的高度與較小推力，但易受到繞線擁塞和元件腳位可繞性降低的影響。
現今業界實體設計（Physical Design）方法和商用工具流程可以使用階層式方法於模組(module)使用特定高度的標準元件，但無法以平坦化方式實現混和高度標準元件實作。另一方面，降低時鐘樹(Clock Tree)功耗可以有效降低整體設計的消耗功率。隨著製程及設計方法的日益演進，經由合併多個單元正反器成為多位元正反器，近年來亦成為減少時鐘面積/功耗之技術之一。
如何在高效能及節能取得一個平衡點，是一個有趣且值得探討的問題，因此本文提出利用平坦化混和高度標準元件實作流程並結合多位元正反器來降低功率損耗 ，並確保電路能到達預定的規格。 本文使用台積電28奈米HPC+製程並以 OpenCores 開源IP 為素材，對不同頻率下高效能積體電路PPA 進行差異性比較及數學模式分析。 | zh_TW |
| dc.description.abstract | For the semiconductor industry, the best solution for high efficiency and energy saving has been constantly researching. In essence, digital integrated circuits can greatly increase product competitiveness if they can reduce power consumption and maximize performance.
In today′s advanced semiconductor processes, standard-cell libraries can be developed with different cell heights, large cell heights (12T) provides higher driving power, but have larger area and power cost. The 7T cell has a small cell area but has weaker drive strengths and routing congestion and pin accessibility issues. Today′s physical design methodology can use hierarchical methods to use standard cells of a particular height in a module, but cannot achieve a mixing height of standard cell implementation in a Traditional flatten physical design flow. On the other hand, reducing the clock power of the Clock Tree can effectively reduce the power consumption of the overall design. With the evolution of process and design methodology, multi-bits flip-flops have become one of the technologies to reduce clock area/power consumption.
To achieve a balance between high performance and energy saving is an interesting and worthwhile question. Therefore, this paper proposes to use mixing high-standard cells implementation methodology with multi-bits flip-flops to reduce power and achieve the predetermined specifications. This paper uses TSMC′s 28nm HPC+ process and uses OpenCores open source IP as the material to compare the difference and mathematical model of high-performance integrated circuit PPA at different frequencies. | en_US |
| DC.subject | 實體設計 | zh_TW |
| DC.subject | 標準元件 | zh_TW |
| DC.subject | Physical Design | en_US |
| DC.subject | Standard Cell | en_US |
| DC.subject | Mix-Cell Height | en_US |
| DC.title | 增進實體設計PPA之混合高度標準元件方法 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Physical Design for PPA with Mix-Cell Height | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |