| dc.description.abstract | Power scaling is one of the major challenges in modern CMOS technology for ultra-low power applications, such as emerging IoT (Internet of Things) technologies and wearable devices. Lowering the supply voltage (VDD) is an efficient technique to achieve ultra-low power consumption for circuits. Device with steep subthreshold slope is essential in order to achieve energy-efficient switching and low leakage power as VDD scaling. Conventional MOSFET exhibits the lower-bound limitation of subthreshold swing (SS) which is about 60 mV/dec at room temperature. In order to tackle this problem, tunneling field-effect transistors (TFETs) have been actively explored [1].
III-V heterojunction TFETs with smaller effective tunneling barrier heights show enhanced on current due to the increased tunneling probability. However, due to the low density of states, III-V heterojunction TFETs exhibit lower on current than the conventioinal MOSFETs at high VDD. However, III-V heterojunction TFETs still show better performance than the conventional MOSFETs at low VDD owing to its steep subthreshold slope.
In the first part of this thesis, the device design and analog performance of GaAs0.49Sb0.51/In0.53Ga0.47As negative-capacitance vertical-tunnel FET (NCVT-FET) are analyzed compared with the vertical-tunnel FET (TFET). The optimized device design of NCVT-FET is proposed to maximize its vertical tunneling over the corner tunneling to reduce its average subthreshold swing. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. The impacts of gate-to-source overlap length, tunnel layer thickness, and N++ doping concentration in the tunnel layer have been investigated. The optimized NCVT-FET exhibits small Ioff (10pA/?m) and large Ion (405?A/?m) at VDD = 0.5V with 14mV/decade subthreshold swing over 4 decades of current. Moreover, the optimized NCVT-FET shows higher transconductance gm,max (+92%), higher gm/IDS, and larger cutoff frequency fT,max (+75%) compared to TFET.
In the second part of this thesis, we analyze the heterojunction GaAs0.4Sb0.6/In0.65Ga0.35As TFET with vertical nanowire structure and non-uniform diameter design (V-NW TFET with non-uniform diameter). A tunnel layer (Tt) is inserted between the gate and source regions for improving the on currents, and the non-uniform diameter thickness is used for suppressing the leakage current (Imin). The bandgap widening induced by quantum confinement is considered in the simulations. The leakage currents can be suppressed by using thinner diameter thickness of the drain/channel junction (TDC), and the gate-to-drain underlap design is used to further reduce the ambipolar leakage. The impacts of Tt, TDC, source and drain doping concentrations, and gate-to-source overlap length (Lsov) on the V-NW TFET have been investigated. Compared with the ultra-thin-body (UTB) TFET, the proposed V-NW TFET with non-uniform diameter (thin TDC) exhibits 2 times larger Ion (236 ?A/μm) due to the increased line tunneling area, and 59.8 times lower leakage current (5.5 × 10-10 ?A/μm). | en_US |