dc.description.abstract | With the development of applications such as artificial intelligence (AI) and Internet of Things (IoT), high-performance components and ultra-low-power systems become more important, and reducing the supply voltage is a way to achieve lower static and dynamic power consumption. However, lowering the supply voltage also reduces the on-current (Ion) of the semiconductor component. Therefore, the steep slope device is necessary for ultra-low power system applications. However, the traditional MOSFETs are limited by the Bozeman distribution at room temperature, and the subthreshold swing cannot be lower than 60mV/dec. Negative Capacitance Field Effect Transistor (NCFET) with better Ion/Ioff ratio is one of the most promising candidate for ultra-low power system.
In this dissertation, the gate-all-around (GAA) stacked negative capacitance nanowire (NC-NW) and nanosheet (NC-NS) FETs are analyzed comprehensively for the first time. Compared with the 3-stacked (3S) NC-NW FET, 1-stacked (1S) NC-NW FET shows larger maximum internal voltage gain (Av,max) due to better capacitance matching, lower minimum subthreshold swing (SS), and larger Ion improvements over nanowire (NW) FET. As the vertically stacked number of NW FETs increases, the effective Ion per unit width decreases due to the increased series resistance. At low gate bias (Vg,ext = 0V to 0.16V), 1S NC-NW FET with larger MOS capacitance (CMOS) with positive ferroelectric capacitance (CFE > 0) shows lower Av (at low Vg,ext) than the 1S NC-NS FET. As gate voltage increases, 1S NC-NW FET enters the negative ferroelectric capacitance region (CFE < 0), and therefore 1S NC-NW FET exhibits higher Av,max than the 1S NCNS FET due to its larger CMOS. Besides, 1S NC-NW FET exhibits +90% Ion improvements over NW FET, and 1S NC-NS FET shows +44% Ion improvements over nanosheet (NS) FET. NW FET exhibits lower DIBL than NS FET due to its better electrostatic control, while NC-NW FET shows more significant negative DIBL than the NC-NS FET due to its larger Av difference between high and low drain bias. NS FET with higher mobility shows larger Ion than the NW FET. However, the Ion difference between NC-NS and NC-NW becomes smaller because NC-NW exhibits larger Av,max.
Second, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on negative capacitance FinFET (NC-FinFET) with P-type and N-type substrates, respectively, compared to FinFET. The trap position dependent RTN amplitude (∆Ids/Ids) along the channel length and fin height directions are examined. Our results show that NC-FinFET exhibits smaller RTN amplitude than FinFET due to its smaller trap induced threshold voltage shift (ΔVT). Besides, for both NC-FinFET and FinFET, N-type substrate shows smaller RTN amplitude and RTN induced ΔVT variations than P-type substrate. In other words, RTN induced variations can be suppressed by substrate doping optimization for NC-FinFET and FinFET.
We investigate the NC-FinFET logic circuits (Inverter, NAND, MUX) considering the impact of supply voltage, interface trap charge, and channel length variation on the delay time. NC-FinFET with higher Ion exhibits lower delay time than the conventional FinFET. The Ion of NC-FinFET slightly decreases when it operates at lower supply voltage, which leads to increasing of the delay time. In addition, NC-FinFET with thinner effective oxide thickness shows better immunity to the surface trap charge induced threshold voltage shift compared to the conventional FinFET. Our results show that the NC-FinFET has better performance in Energy Delay Product (EDP) compared to the conventional FinFET at low supply voltage. | en_US |