| dc.description.abstract | 隨著元件尺寸微縮，具低功耗與高性能特性的元件對於現階段積體電路系統是非常重要，降低操作電壓(Supply Voltage)為降低功耗最有效的解決方法之一。而當降低元件操作電壓時，伴隨著降低元件導通電流(On Current)的缺點，因此具有陡峭次臨界擺幅(Subthreshold Swing)與較高開關電流比值(Ion/Ioff ratio)的負電容場效電晶體(Negative Capacitance Field Effect Transistor, NCFET)，為有機會實現低功率消耗與高性能的前瞻元件之一。
第一部分利用TCAD結合穩態的Landau-Khalatnikov方程式，建立了負電容絕緣層上矽場效電晶體的數值模擬流程架構，分析負電容絕緣層上矽場效電晶體的類比品質因數(Analog Figures-of Merit)，並且考慮變異度對於類比品質因數的影響。在類比品質因數的研究中，負電容絕緣層上矽場效電晶體比絕緣層上矽場效電晶體在轉導(Transconductance, gm)、汲極電流轉換效率(Drain Current Efficiency, gm/Id)皆有顯著提升，並表現出相近的截止頻率(Cutoff Frequency, ft)。接著，探討類比品質因數考慮變異度對於負電容絕緣層上矽場效電晶體和絕緣層上矽場效電晶體的汲極輸出電阻(Drain Output Conductance, gd)、轉導、汲極電流轉換效率與截止頻率之影響，變異度包含線邊緣粗糙變異度(Line Edge Rouoghness, LER)和金屬功函數變異度(Work Function Variation, WFV)。負電容絕緣層上矽場效電晶體在考慮線邊緣粗糙度所引起的汲極電流與汲極輸出電阻變異度，小於考慮金屬功函數變異度所引起的汲極電流與汲極輸出電阻變異度，然而對於轉導、汲極電流轉換效率及截止頻率變異度為相反的趨勢，這是由於考慮線邊緣粗糙度的電壓增益的變異度比考慮金屬功函數的電壓增益變異度大。
第二部份為負電容絕緣層上矽場效電晶體考慮表面陷阱電荷(Interface Trap Charge, Nit)與閘極長度變化應用於類比電路的研究，此部分利用TCAD軟體考慮Landau-Khalatnikov的模型在混合模式(Mixed-Mode)下模擬其電路特性。探討三種電路，分別為電容放電(Discharging Circuit)、類比開關(Analog Switch)以及電流鏡(Current Mirror)。相較於絕緣層上矽場效電晶體，負電容絕緣層上矽場效電晶體提升電容放電速度、具有較小的導通電阻(On Resistance)，並改善平坦度(Flatness)，以及降低輸出電流(Iref)誤差率。另外，負電容絕緣層上矽場效電晶體可以抑制變異度對放電速度、導通電阻以及輸出電流的變化，研究結果顯示負電容絕緣層上矽場效電晶體可以簡化堆疊式電流鏡電路，同時保持與堆疊式電流鏡電路相近的輸出電流準確度。 | zh_TW |
| dc.description.abstract | As the semiconductor device scales, device with ultra-low power and high performance is essential to vary-large-scale integration system. Lowering the supply voltage is the most effective way to reduce the power consumption. However, transistors show worse drive current and performance with the supply voltage lowering. Therefore, device with steep subthreshold slope is essential in order to achieve high Ion/Ioff ratio and low power as supply voltage scales. Negative capacitance field effect transistor (NCFET) is promising candidate to achieve low-power consumption and high performance.
In the first part, we establish the numerical simulation framework for NCFET by using TCAD coupled with Landau-Khalatnikov equation, and then we analyze the variability of analog figures-of merit (FOMs) for negative capacitance FETs. Negative capacitance SOI MOSFETs (NC-SOI MOSFETs) exhibit larger transconductance (gm), larger drain current efficiency (gm/Id), and comparable cutoff frequency (ft) compared with the SOI MOSFETs. For the variability study, we analyze Id-Vds characteristics and analog figures-of merit (FOMs) for NC-SOI MOSFETs and SOI MOSFETs considering line-edge roughness (LER) and work function variation (WFV). For NC-SOI MOSFETs, LER induced Id and drain output conductance (gd) variations are smaller than WFV induced Id and gd variations, because LER induced σVt is smaller than WFV induced σVt. However, the variability of other analog figures-of merit such as gm, gm/Id, and ft for NC-SOI MOSFETs considering LER and WFV show different trend as compared to σVt. NC-SOI MOSFETs considering WFV exhibit smaller σgm, σ(gm/Id), and σft than NC-SOI MOSFETs considering LER, due to the smaller WFV induced internal voltage gain (Av) variations.
In the second part, we analyze the circuit performance of NC-SOI and SOI MOSFETs considering the impact of interface trap charge (Nit) and gate length (Lg) variations. NC-SOI analog circuits are analyzed by TCAD mixed mode simulations employing Landau-Khalatnikov equation. Compared to SOI MOSFETs, NC-SOI MOSFETs show significant improvements in discharging time (ts), lower on resistance (Ron) and better Ron flatness, and better output current (Iout) matching. For NC-SOI MOSFETs, the discharging time, Ron of switch circuit, and Iout of current mirror show superior immunity to Nit and Lg variations compared to the SOI counterparts. Moreover, NC-SOI current mirror can significantly reduce the circuit complexity and area penalty while maintaining adequate mirroring accuracy compared to the stacked SOI current mirror. | en_US |