| dc.description.abstract | Currently, the layouts of analog circuits are often generated manually. In order to speed up analog design cycles, analog layout automation is a popular research in recent years. Due to the sensitivity of analog circuits, it is important to consider non-ideal effects in design stage by setting proper layout constraints. However, most of the layout constraints are given manually in current design flow, which requires lots of time. Template-based layout generation is a possible approach to consider the design constraints automatically, but considerable development efforts are required for each new design or technology. Therefore, an integrated layout automation tool including placement, routing and constraint generation could be helpful to reduce design time.
This thesis proposes a structure-based methodology for analog layout generation. This methodology starts from a structure analysis that divides the circuit netlist into several building blocks automatically. It can help to reduce the dependence on users’ input and generate corresponding design constraints for the succeeding layout steps. With the help from structure analysis, the layouts of those analog structures are generated, placed, and routed automatically with proper constraints. As shown in the demo cases, the proposed flow is able to generate the required layout accurately without users’ intervention and still keeps the post-layout performance within specifications.
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