| dc.description.abstract | As the process continues to scaling, chip size is getting smaller, but the number of transistors on the chip is increasing. This significantly increases the difficulty for designing such complicated chips. In addition, due to the strong needs for low-power equipments, such as notebook computers, wearable devices, etc…, extending battery life and reducing heat dissipation become important considerations for such high-density designs. However, transistor-level power estimation becomes very complicated and slow for large designs. Therefore, proper high-level power modeling methods are required to evaluate the power consumption at design stages.
In order to support the needs for In Memory Computing, this thesis proposes a high-level power consumption model for this special memory. Unlike traditional memory power models that can provide only the same value for different access, the proposed power model considers the effects of different address and data, and provides distinct power values for different input patterns. According to different operation modes, different regression approaches are proposed for memory read and write to construct accurate power models. According to the experimental results, the average error for different access modes can be controlled within 10%, and the simulation time is greatly reduced. After combing the proposed power model and the system –level simulator Gem5, a simple but complete program also demonstrates the capability to support high-level simulator. | en_US |