| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 陳昱均 | zh_TW |
| DC.creator | Yu-Jun Chen | en_US |
| dc.date.accessioned | 2021-1-22T07:39:07Z | |
| dc.date.available | 2021-1-22T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=106521058 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文呈現模擬車用下世代十億位元乙太網路通訊環境之訊號還原演算法設計與等化器電路實踐，此網路通訊所規定的規格IEEE 802.3bp™-2016採用非屏蔽雙絞乙太網路線來傳輸PAM-3編碼之訊號。乙太網路線因為存在著通道頻寬的關係而通道訊號內部擁有符碼間干擾（ISI），為了減輕符碼間干擾的影響，需要使用自適應數位纜線通道等化器來還原乙太網路線接收到的訊號。
然而由於車內環境的緣故，除了一般通訊設備會遇到的高斯白雜訊之外，射頻干擾雜訊也是一個重要的訊號雜訊。因此，本論文選擇非強制頻域前饋式等化器結合時域決策回授等化器嘗試減緩射頻干擾雜訊之影響，時域決策回授等化器用來消除後符碼間干擾，而非強制頻域前饋式等化器除了消除前符碼間干擾外，之後的章節也會進而探討此等化器用於減緩車內的射頻干擾雜訊之影響可行性。此外，通道等化器及時序迴路會發生交互作用，因而造成時序回復電路時序產生發散的情況發生，本論文有針對此議題提出討論及解決。硬體實現上使用製程為TSMC 40nm透過Design Compiler 及IC Compiler 進行數位電路的時序模擬與電路布局模擬，最後也使用相同製程來設計晶片。 | zh_TW |
| dc.description.abstract | The purpose of this study was to simulate the environment of the next-generation Gigabit Ethernet communication in vehicles to develop an equalization algorithm, architecture, and the equalizer circuit design. In the IEEE 802.3bp™-2016, the PAM-3 encoded signals are transmitted by unshielded twisted pair cable. Due to the limitation of cable bandwidth, there is inter-symbol interference (ISI) between the signals in the Ethernet cable. In order to mitigate the impact of inter-symbol interference, an adaptive digital cable channel equalizer is needed to equalize the signal through the Ethernet cable.
In addition to the normal additive white Gaussian noise (AWGN) influencing the signals in the communication systems, radio frequency interference is also a huge noise in the environment of the car. A main topic of this thesis is to discuss whether the architecture of Unconstrained Frequency Domain Feed Forward Equalizer combining with a time domain decision feedback equalizer can be a better solution of eliminating the radio frequency interference comparing with the normal Time Domain Feed Forward Equalizer. Besides, the channel equalizer and the timing loop will cause the timing recovery circuit to diverge due to their interaction. This paper will also discuss and solve this issue. The hardware implementation process uses TSMC 40nm to perform timing simulation and circuit layout simulation of digital circuits through Design Compiler and IC Compiler. Finally, the same process is used to implement the chip. | en_US |
| DC.subject | 頻域等化器 | zh_TW |
| DC.subject | 時序回復 | zh_TW |
| DC.subject | 射頻干擾 | zh_TW |
| DC.subject | 車用乙太網路 | zh_TW |
| DC.subject | VLSI | zh_TW |
| DC.title | 適用於1Gbps車用乙太網路傳輸之頻域等化器電路與時序回復電路實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Frequency Domain Equalizer and Timing Recovery Circuit Design for Giga-bit Automotive Ethernet Receiver | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |