| dc.description.abstract | In modern communication systems, in order to meet the demand for high data rate wireless communication the advantage of the high operating bandwidth of the radio frequency (RF) transceiver system is also apparent. The local oscillator (LO) source is very important as the role of upconversion/downconversion in the system. One challenge facing such systems is the strict phase-noise requirements of the local oscillator (LO). The LO phase noise adds directly to the received signal and results in limited overall system performance. The phase-locked loop (PLL) proposed in this paper can accurately provide a stable frequency. The injection locking technology can be employed to effectively reduce the phase noise. The total locking range is enhanced with a divider-less architecture to achieve a quadrature oscillator with wide locking range, low power consumption, low phase noise, and low jitter.
The Chapter 2 is the X-band multi-phase phase-locked loop. The PLL is using TSMC 0.18 μm CMOS process design and implementation. The building blocks of the presented PLL is composed of a QVCO, a phase-frequency detector, a charge pump, a loop filter and two-stage common-mode logic dividers and four-stage true single-phase clocking dividers. This circuit has the phenomenon of loop oscillation, but through the external second-order filter, it has a successful locking frequency. The debug for the proposed PLL is also presented in this chapter with the simulated results. The chip size is 1.06 × 0.8 mm2. The simulated frequency is 9.3 GHz to 10.8 GHz. The measured frequency is from 9.49 GHz to 9.52 GHz. The output power is close to -3 dBm. The measured phase noise is -96 dBc/Hz at 1-MHz offset. The total DC power consumption is 60.4 mW. In addition, the effect of loop bandwidth is also addressed to improve the phase noise of the PLL.
In Chapter 3, a subharmonic-injection locked frequency-locked loop with the advantages of low phase noise and low jitter is adopted. The subharmonic-injection locking technology is introduced. By using the transformer coupling architecture, the injection locking oscillator has better performance. The frequency locking loop is designed using divider-less loop, the overall phase noise and jitter can be properly designed using the presented linear model of the frequency-locked loop, and the design of the presented subharmonic-injection frequency locking loop is completely presented with the simulated results to further reduce the output phase noise and jitter. The circuit is designed using TSMC 65 nm CMOS process, the chip size is 1 × 0.7 mm2. The measured overall frequency locking range is from 30 GHz to 36.6 GHz. The average output power is about -9 dBm. The phase noise is -130.3 dBc/Hz at 1-MHz offset. The RMS jitter (integrated from 1 kHz to 40 MHz) is 8.7 fs. The phase error and amplitude error are 0.9˚ and 0.43 dB, respectively, and the total DC power consumption is 31.3 mW.
In Chapter 4, we introduce the W-band subharmonic injection locked quadrature VCO with divider-less frequency tracking loop. First, we introduce the theoretical model and transfer function. Then we use ADS (advance design system) software to simulate and analyze the frequency locking loop, which can effectively analyze the open loop and closed loop response of the frequency locking loop system. In addition, the theoretical model is used to analyze and compare the phase noise and jitter of various structure frequency synthesizers. The circuit is using TSMC 40 nm CMOS process. The chip size is 0.982 × 0.86 mm2. The simulated VCO frequency is 91.6 GHz to 96.7 GHz. The measured VCO frequency is 98.2 GHz to 102.6 GHz. The phase noise is - 93.3 dBc/Hz at 1-MHz offset. If the frequency is seriously offset from the analog to the high frequency, it will be debugged in this chapter. | en_US |