dc.description.abstract | Phased array is commonly used in radar systems for beam steering. In 5th generation mobile communication system that will be deployed soon, phased array also plays an important role. Phase shifter, used for providing tunable phase shift, is one of the essential circuit components in phase arrays. In this thesis, two types of phase shifters, which are passive phase shifter based on magnetically coupled all-pass networks and vector-summing active phase shifter using area-resizing technique, are proposed. The phase shifters are realized in integrated circuit form and operate in S-band.
All-pass networks have been used in phase-shifter design. Magnetically coupled all-pass network (MCAPN) with positive coupling coefficient may be used to increase the amount of phase shift. In Chapter 2 of this thesis, a 2.45-GHz 5-bit passive phase shifter is designed based on MCAPN with positive coupling coefficient. The design goal is to achieve 180° phase shift with only one stage of network. The switched capacitors in the phase shifter are implemented using TSMC 0.18-μm CMOS technology. The coupled inductors are realized on a silicon carrier substrate using an integrated passive device (IPD) process. Finally, the phase shifter is completed by assembling the CMOS chip and IPD carrier substrate with flip-chip bonding. Measurement results show that, if the switched capacitors are controlled in the originally intended way, the phase shifter exhibits 179.4° phase shift at 2.45 GHz but the return loss is however not greater than 10 dB for all 32 states. If the controlling bits for individual switched capacitors are properly modified, ending up in 23 sets of states, then at 2 GHz, the return loss is greater than 10 dB and the insertion loss is less than 14.5 dB for these 23 sets of states. The phase shift achieved is 147.8° at 2 GHz.
Vector-summing architecture is usually adopted for the design of active phase shifters. In Chapter 3 of this thesis, a 3.5-GHz 6-bit vector-summing active phase shifter is designed in TSMC 0.18-μm CMOS. In addition, area-resizing technique is adopted for the design of the variable gain amplifiers (VGAs) in the vector-summing phase shifter. The advantage of the area-resizing technique is that the phase and amplitude errors may be indefinitely reduced by increasing the number of the controlling bits of the VGAs. Measurement results show that, from 3.3 to 3.8 GHz, the rms phase error is less than 1.15° and the amplitude error is within ±0.45 dB. For all 64 states, the input return loss is greater than 15 dB, the output return loss is greater than 7.9 dB, and the gain is greater than −8.81 dB. Moreover, between 2.46 and 4.68 GHz, the rms phase error is less than 2°.
Quadrature generation network is a necessity in vector-summing phase shifter. Common quadrature generation networks include R-C poly-phase filter and quadrature all-pass filter (QAF). In Chapter 4 of this thesis, QAF with magnetic coupling is proposed for reducing the chip area. 1.8–2.2 GHz QAFs are implemented using a GaAs-based IPD process. Measurement results show that, given that the circuit performances are similar, the magnetically coupled QAF (MCQAF) occupies a chip area of 0.101 mm2 whereas conventional QAF occupies 0.154 mm2. This translates into a 34% reduction in chip area.
In this work, S-band passive and active digital phase shifter chips are successfully realized and MCQAF is proposed. Among them, the vector-summing phase shifter that adopts area-resizing technique exhibits competitively low phase and amplitude errors. Besides, it is also demonstrated that the proposed MCQAF could considerably save chip area.
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