| dc.description.abstract | The purpose of this thesis is to design a power amplifier (PA) for the front-end of transceiver. Including a power amplifier for Ku band and three power amplifiers for Ka band. Power amplifier is an important component in RF system. In the front-end circuit of the transmitter, the RF signal power generated by the modulation is very small, and it needs a series of amplifier stages to obtain sufficient RF power to radiate by antenna. Therefore, it is necessary to have a power amplifier with high stability, high efficiency and high saturation output power in the transmitter system.
In Chapter 2, a Ku-band power amplifier using WIN 0.25 μm GaN process for digital satellite broadcasting application is presented. With two-stage topology and Class-E output matching network, the proposed can improve the overall power gain, and achieve high power-added efficiency (PAE). The measurement current is about one third less than the simulation. The small signal peak gain is 13.4 dB at 10.3 GHz, and 3-dB bandwidth from 9 GHz to 12.3 GHz. As the frequency 12 GHz, the simulated saturation output power (Psat) of 34.5 dBm, the peak PAE of 37.2 %. The power consumption is 7.26 W, and the chip size is 2.5×2 mm2.
In Chapter 3, the analysis of the stability is presented to solve the low-frequency oscillation. Two Ka-band power amplifiers for 5G (fifth generation mobile communication) application, using WIN 0.1 μm GaAs (P1010) and WIN 0.15 μm GaAs (P1522) processes. The power amplifier is designed using binary power combine and T-model matching network. With a dc power consumption of 3.11 W, the proposed power amplifier features small signal gain of higher than 8.5 dB, 1-dB gain compression point output power of 24 dBm, saturation output power of 25 dBm. The chip size of the power amplifier is 2.5×2 mm2. With the power amplifier of neutralization topology, the measured small signal gain is 13.6 dB, the 3-dB bandwidth from 26.6 GHz to 30.6 GHz. The simulated output power at 1-dB gain compression point is 24.3 dBm, the saturated output power is 26.2 dBm, the peak PAE is 23%. The power consumption is 1.34 W, the chip size is 2×1 mm2.
In chapter 4, a Ka-band three-stage power amplifier using pre-matching output network is designed by WIN 0.15 μm GaAs (P1555) process. By using this kind of output matching network can be equivalent to a single high impedance transmission line, the conversion from low impedance to high impedance can increase the 3-dB bandwidth and reduce the loss of the matching network. Each stage series a RC in parallel to improve stability, the first and second stages increase the power gain of the circuit, and the third stage combines four transistors in parallel as the power stage to obtain a higher output power. Odd-mode resistance is also used to prevent odd-mode oscillation. The measured small signal gain is 16.9 dB, the 3-dB bandwidth is from 24.5 GHz to 30.7 GHz. the simulated output 1-dB gain compression point is 29.2 dBm, the saturated output power is 32.2 dBm, the power consumption is 9.81 W, the chip size is 3×2 mm2.
Finally, in Chapter 5 we try to summarizes the proposed circuits and discuss the future research direction. | en_US |