| dc.description.abstract | 隨著物聯網(Internet of things, IoT)、人工智慧(Artificial Intelligence, AI)和邊緣運算(Edge Computing)的興起，高效能並具備低功耗之記憶體變成一個受歡迎的研究主題。使用二氧化鉿(HfO2)之鐵電場效電晶體(FeFET)具備了一些優點，例如低功率消耗、非揮發性(non-volatile)、微縮性(Scalability)和與CMOS製程相容等優勢，因此鐵電場效電晶體有望成為下一世代非揮發性記憶體之候選者。變異度一直都是所有元件所存在的議題，因為會影響到元件的效能。目前關於金屬功函數變異度對鐵電場效電晶體記憶體的影響，尚未有完整的研究，本論文將利用MATLAB考慮金屬晶粒之數量與位置波動，並且結合TCAD模擬，深入探討金屬功函數變異度及鐵電材料層之介電相-鐵電相分布，並分析對鐵電記憶體之高低阻態臨界電壓及記憶體視窗(Memory window)影響。
本論文研究鐵電記憶體元件考慮金屬功函數變異度之影響，研究結果顯示改變金屬閘極晶粒尺寸、閘極面積和鐵電參數對記憶體視窗變異度沒有顯著的影響，因為有相同的極化平移量(ΔP)，但利用金屬閘極晶粒尺寸和閘極面積仍可以改善高和低臨界電壓變異度，改變金屬閘極晶粒尺寸從10 nm到2 nm，高臨界電壓變異度從53.7 mV變成15.6 mV，而低臨界電壓變異度從53.1 mV變成16.2 mV;閘極面積從Lg × W = 20 nm × 20 nm變為Lg × W = 35 nm × 35 nm，高臨界電壓變異度從23.8 mV變成16.6 mV，而低臨界電壓變異度從24.1 mV變成15.1 mV。
此外，本論文亦分析鐵電材料層之介電相-鐵電相分布之影響，當鐵電材料層包含鐵電相(正交晶系, Orthorhombic)和介電相(如四方晶系, Tetragonal、單斜晶系, Monoclinic)的非均勻分布時，將影響鐵電記憶體之記憶體視窗變異度。因此，我們分析金屬功函數變異度結合鐵電變異度(介電相-鐵電相分布)對鐵電電晶體的影響，當改變閘極面積從Lg × W = 20 nm × 20 nm變為Lg × W = 35 nm × 35 nm，記憶體視窗變異度從37.6 mV變為12.3 mV;當提升鐵電相比例從50%到75%，記憶體視窗變異度從37.6 mV變為13.9 mV，結果顯示當鐵電材料層有較高及均勻的鐵電相分布時，能改善其記憶體視窗變異度。 | zh_TW |
| dc.description.abstract | With the rise of the Internet of Things (IoT), Artificial Intelligence (AI) and Edge Computing, high performance and low power consumption memory have become popular research topics. Using hafnium dioxide (HfO2) on FeFET shows several advantages such as low power consumption, non-volatility, scalability, and CMOS compatibility, thus the FeFET has become a promising candidate for the next-generation non-volatile memory. Variability has always been an issue for all devices because it affects the device performance, however, the impact of work function variation for ferroelectric FET memory has rarely been examined. This thesis uses MATLAB considering the metal grain number and position fluctuation, and uses TCAD simulation to discuss the impact of work function variation for the high and low threshold voltage and memory window of ferroelectric FET memory.
Our thesis analyzes the impact of work function variation on FeFET memory. Our results show that changing the metal grain size, gate area, and ferroelectric parameters do not affect memory window variation (σMW) significantly due to the same ΔP. However, as the metal grain size reduces and the gate area increases, the high and low threshold voltage variations caused by work function variation can be improved. As the metal grain size reduces from 10 nm to 2 nm, the high threshold voltage variation changes from 53.7 mV to 15.6 mV, and the low threshold voltage variation changes from 53.1 mV to 16.2 mV. As the gate area increases from Lg × W = 20 nm × 20 nm to Lg × W = 35 nm × 35 nm, the high threshold voltage variation changes from 23.8 mV to 16.6 mV, and the low threshold voltage variation changes from 24.1 mV to 15.1 mV.
In addition, when the FE grains (orthorhombic phase) are not uniformly distributed, and there exists tetragonal and monoclinic phases that may form dielectric (DE) as high-k oxide, the non-uniform dielectric-ferroelectric (DE-FE) phase distributions will affect the memory window variations. Therefore, we analyze the combined effects of work function variation and ferroelectric variation (DE-FE phase distribution) on the FeFET memory. Our results show that as the gate area increases from Lg × W = 20 nm × 20 nm to Lg × W = 35 nm × 35 nm, σMW changes from 37.6 mV to 12.3 mV. As the ferroelectric percentage increases from 50% to 75%, the σMW changes from 37.6 mV to 13.9 mV. Our results show that the σMW can be improved by increasing the percentage of FE phase. | en_US |