| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 蔡采玲 | zh_TW |
| DC.creator | Tsai-Ling Tsai | en_US |
| dc.date.accessioned | 2021-10-12T07:39:07Z | |
| dc.date.available | 2021-10-12T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=107521031 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 大多現代計算機系統是建立在 馮紐曼(von Neumann)架構上，也就是架構上記憶體及處理器是分開來的，當資料在這兩者之間做搬移時，會造成能量的耗損以及遭遇表現上的限制，尤其是面對需要大量資料處理的應用，內存計算(CIM)是一種為解決這種瓶頸而提出的解決方式，CIM記憶體有記憶體模式與計算(computing)模式。現今已有多種靜態隨機存取記憶體(SRAM)單元(cell)及SRAM的模型用來實現CIM。這使得測試CIM記憶體比測試傳統記憶體更為困難。在此篇論文我們提出一個測試CIM SRAM的方法，包括比較缺陷(defect)導致的故障(fault)模型，還有如何發展測試演算法。一開始我們會先介紹CIM SRAMs在記憶體模式與計算模式中建立故障模型的方式，接著比較缺陷在這兩種模式導致的故障模型，最後介紹如何發展CIM SRAM的測試演算法。我們所提出的方法會使用8T及10T SRAM單元作個案討論。具有8T和10T SRAM單元的CIM SRAM的故障是透過注入電氣缺陷來定義的，接著比較在記憶體模式和計算模式中發生的故障模型，最後針對記憶體模式與計算模式的故障分別開發了測試演算法。 | zh_TW |
| dc.description.abstract | Most modern computer systems are based on von Neumann architecture, which separates the memory and the processor. The data movement between the memory and the processor
limits the performance and power consuming, especially for data-intensive applications. Computing-In-Memory (CIM) architecture is one possible approach to cope with the bottleneck. A CIM memory can be operated in memory mode or computing mode. Also, various memory cells were proposed to realize CIM memories. Those make the testing of CIM memories
to be more difficult than that of conventional memories. In this thesis, we propose a test methodology for CIM SRAMs, including fault modeling, fault collapsing by defects, and
test development. A fault modeling method of CIM SRAMs in memory mode and computing mode is introduced first. Subsequently, faults in memory mode and computing mode are collapsed by defects. Then, a test development method for CIM SRAMs is introduced. The proposed test methodology applied to CIM SRAMs with 8T and 10T SRAM cells are presented as case studies. Faults of the CIM SRAMs with 8T and 10T SRAM cells are defined by injecting electrical defects. Then, faults occur in both memory mode and computing mode are collapsed by defects. Finally, test algorithms are developed for the faults in memory mode and computing mode. | en_US |
| DC.subject | 靜態隨機存取記憶體 | zh_TW |
| DC.subject | 記憶體測試 | zh_TW |
| DC.subject | 錯誤模型 | zh_TW |
| DC.subject | SRAM | en_US |
| DC.subject | memory testing | en_US |
| DC.subject | computing-in-memory | en_US |
| DC.subject | CIM | en_US |
| DC.subject | Fault model | en_US |
| DC.title | 基於靜態隨機存取記憶體的內存計算記憶體測試 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Testing of SRAM-Based In-Memory-Computing Memories | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |