| dc.description.abstract | With the rapid development of information and communication industries such as cloud computing, edge computing, and artificial intelligence in recent years, the demand for computing power has increased rapidly, and the requirements for data transmission speed and environmental noise complexity have also increased. However, as the transmission speed increases, the data is more seriously affected by the transmission distance, and the proportion of noise in the total signal also increases, resulting in a decrease in signal quality. Therefore, it is very important for equalizers to restore the integrity of the signal in the transmission process.
This paper proposes a signal Self-Reference generation technology to assist in the logical judgment of single-ended input data. It uses the voltage level change direction of the data amplitude to judge the data polarity. By using an innovative Track-Extend-Regenerate Slicer to solve the continuous data problem, the self-reference generation technology is realized to save hardware complexity and improve the adaptability of the equalizer to high-noise environments. In addition, it is combined with an adaptive system to ensure that the Self-Reference generation technology can assist the adaptive system and DFE to compensate the signal reasonably in high noise and high channel-loss environments, and restore the correct data.
This paper is implemented using TSMC 90 nm (TN90GUTM) 1P9M CMOS process. The circuit operating voltage is 1 V. The input data rate is 10 Gbps single-ended NRZ data signal. The input clock adopts a single-ended 5 GHz clock signal, and a half-rate differential 5 GHz clock signal is generated by the internal circuit. The equalizer can be used in a noisy environment with a maximum channel-loss of 24 dB. When the input data amplitude is 250 mV, the maximum low-frequency sine wave (100 MHz) noise amplitude that can be resisted is 50 mV. After the signal Self-Reference generation technology equalizer restores the 10 Gbps single-ended NRZ data signal, the post-layout simulation shows that the peak-to-peak jitter of the restored data is 27.63 ps when the channel-loss is 14 dB. The post-layout simulation shows that the peak-to-peak jitter of the restored data is 22.51 ps when the channel-loss is 24 dB. The overall power consumption is 43.97 mW, of which the power consumption of the equalizer CTLE, 1-tap SR DFE, and Track-Extend-Regenerate Slicer is 19.73 mW, and the power consumption of the adaptive system is 24.24 mW. The overall area is 0.9 × 0.9 mm2, of which the area of the core circuit is approximately 0.103 mm2. | en_US |