| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 楊芷昕 | zh_TW |
| DC.creator | Chih-Hsin Yang | en_US |
| dc.date.accessioned | 2020-8-17T07:39:07Z | |
| dc.date.available | 2020-8-17T07:39:07Z | |
| dc.date.issued | 2020 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=107521041 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著製程不斷的演進，電路佈局時的非理想效應，也對敏感的類比電路帶來越來越多挑戰，然而，目前類比電路佈局的自動化工具仍然不足以支援設計者需求。為了減少電路佈局後的性能受到影響，勢必需要優化傳統的佈局流程，因此本論文提出的類比電路佈局擺置流程，希望能夠同時考慮先進製程中的淺溝槽效應(Shallow trench isolation, STI)以及佈局擺置後所需的繞線空間，降低非理想效應對電路性能的耗損。
給定一個初始的電路擺置拓樸，本論文提出一個類比電路佈局擺置微調的自動化流程，同時考慮考量淺溝槽應力所需要的距離限制，以及佈局繞線時所需要的空間，透過重新配置電晶體的位置，本論文也提出了一個減少繞線轉彎線段演算法，如同實驗所示，使用本論文提出的擺置微調方法後，相較於傳統的佈局演算法，繞線溢出及導孔的使用數量均有明顯的改善，更加優化佈局繞線後的品質。 | zh_TW |
| dc.description.abstract | As the process technology continues scaling down, the increasing layout dependent effects bring more and more challenges to sensitive analog designs. Unfortunately, designers are still not satisfied with the tool-generated analog layouts. In order to reduce the performance impact from layout, it is necessary to optimize the traditional layout algorithms. Therefore, our target in this thesis is to consider the shallow trench isolation effect in advanced manufacturing processes and routing resource preservation simultaneously at placement stage. This can help to reduce the loss of circuit performance caused by non-ideal effects.
Based on a given initial circuit placement topology, this thesis proposes a placement refinement technique for analog layout to consider the distance constraints for shallow trench stress effect and the routing space preservation simultaneously. Through reconfiguring the position of transistors, another technique is proposed to reduce the number of bending segments in the routing results. As shown in the experimental results, the proposed placement flow can efficiently reduce the routing overflow and number of used vias in the final layout, which greatly improves the layout quality. | en_US |
| DC.subject | 佈局 | zh_TW |
| DC.subject | 可繞度 | zh_TW |
| DC.subject | layout | en_US |
| DC.subject | routability | en_US |
| DC.title | 考量可繞度及淺溝槽隔離效應之類比佈局擺置微調方法 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Placement Refinement Methodology for Analog Layout Considering Routability and STI-Stress Effect | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |