| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 蔡忠穎 | zh_TW |
| DC.creator | Chung-Ying Tsai | en_US |
| dc.date.accessioned | 2021-9-16T07:39:07Z | |
| dc.date.available | 2021-9-16T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=107521053 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文依據IEEE 802.3bz™-2016規範標準[1]，設計出乙太網路傳輸之數位基頻收發機晶片來送收PAM-16編碼之訊號。有線乙太網路通道屬於緩慢時變通道，因此提出通道等化器演算法、時序恢復電路及數位電路設計，在演算法的選擇上使用較低複雜度的LMS演算法來解決通道效應。其中通道等化器採用前饋等化器（Feedforward Equalizer, FFE）、決策回饋等化器（Decision Feedback Equalizer, DFE）、湯林森-何洛緒瑪預編碼（Tomlinson-Harashima Precoder , THP）[2][3]以及輔助回授等化器（Auxiliary Feedback Equalizer, AFBE）[4]做設計。為解決時脈不匹配效應以及通道的角度偏移效應，以鎖相迴路設計之時序恢復電路（Timing Recovery）採用穆勒與姆勒演算法（Mueller and Muller, M&M）的相位檢測方法實現，並透過粒子群最佳化演算法（Particle Swarm Optimization Algorithm, PSO）[5]來選擇通道偏移的角度，其目的在找到較好的通道角度以提升其效能。在硬體實現上，先利用Verilog HDL撰寫，透過SMIMS VeriEnterprise Xilinx FPGA進行即時驗證電路功能，且經由Design Compiler來驗證在製程選擇為TSMC 40 nm下的電路功能，最後也使用相同製程來實現晶片。 | zh_TW |
| dc.description.abstract | This work designs the digital baseband transceiver for Ethernet transmission using PAM-16 signal based on standard IEEE 802.3bz™-2016. The wired Ethernet cables are slow time-varying channels while high speed signals transmitted. Thus, the channel equalizer, timing recovery circuit and the related digital circuit design are proposed to solve the channel effect with lower complexity LMS algorithm. The channel equalizer adopts the feedforward equalizer, decision feedback equalizer, Tomlinson-Harashima Precoder and auxiliary feedback equalizer. In order to solve the clock mismatch effect and the channel angle offset effect, the Timing Recovery circuit designed with a phase-locked loop is implemented using the Mueller and Muller algorithm. Furthermore, the Particle Swarm Optimization Algorithm (PSO) is used to select the channel offset in purpose to find a better channel angle to increase its effectiveness.
At last, this hardware design is coded in Verilog HDL and simulated. The circuit function is verified in real time through SMIMS VeriEnterprise Xilinx FPGA, and implemented under TSMC 40nm process through Design Compiler, and finally use the same process to complete the chip. | en_US |
| DC.subject | 等化器 | zh_TW |
| DC.subject | 時序恢復 | zh_TW |
| DC.subject | Equalizer | en_US |
| DC.subject | Timing Recovery | en_US |
| DC.title | 運用粒子群最佳化演算法之自適應等化器與時序恢復電路設計 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design of Adaptive Equalizer and Timing Recovery Circuit with Particle Swarm Optimization Algorithm | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |