| dc.description.abstract | In modern communication systems, in order to meet the demand for high-speed data transmission, the advantages of the wide bandwidth of the radio frequency transceiver system have also emerged. The local oscillator source plays an important role in the system. The local oscillator source has very strict requirements for phase noise. If the phase noise is high, the signal-to-noise ratio of the transceiver degrades, as well as system performance. The phase-locked loop proposed in this paper can accurately provide stable frequency, and the injection-locking technology can effectively reduce phase noise. Moreover, a frequency-locked loop with a divider-free feedback can be adopted to widen locking range and reduce dc power consumption, phase noise, and jitter.
A X-band multi-phase phase-locked loop is presented in Chapter 2. The circuit is designed and implemented using TSMC 0.18 μm CMOS process. The phase-locked loop includes a transformer-coupled voltage-controlled oscillator, a phase-frequency detector, a charge pump, a loop filter, two current-mode frequency dividers, and four true-single-phase-clock frequency dividers. Due to the frequency offset of the voltage-controlled oscillator, the power output to the frequency divider is insufficient, resulting in only half frequency range of the phase-locked loop functioning normally. The measured frequency range of the oscillator is from 8 to 8.67 GHz, and the measured frequency range of the phase-locked loop is from 8.2 to 8.67 GHz, and the output power is -5 dBm under the free-running condition. The measured output phase noise at 1 MHz offset is -102.7 dBc/Hz, and the DC power consumption is 44.6 mW.
A sub-harmonically injection-locked frequency-locked loopis presented in Chapter 3, and it features low phase noise and jitter. First, the sub-harmonically injection-locked technology is introduced. By using a transformer-coupled architecture with a stacked boosting, the injection-locked oscillator can have better characteristics up to 28 GHz. The oscillation core can increase the negative resistance without using more power consumption. According to the calculated method of the system simulation phase noise linear model, it can be known that when the oscillator lock bandwidth is sufficient, the overall frequency lock loop can obtain lower output phase noise. Its operating frequency ranges from 24.7 to 27.1 GHz. When the frequency of the frequency-locked loop is 25.5 GHz, the measured phase noise at 1-MHz offset is -130 dBc/Hz, and thethe measured jitter integrated from 1 kHz to 40 MHz is 15 fs, the amplitude error and phase error are 0.2 dB and 0.1°, respectively, and the overall DC power consumption is 55.8 mW.
Chapter 4 introduces a 2n-QAM 38-40 GHz IQ modulator using sub-harmonically injection-locked frequency locked-loop, and the circuit is designed using TSMC 90 nm CMOS process. Due to the divider-less topology, it has lower dc power consumption, phase noise, and jitter. The proposed IQ modulator consists of a quadrature sub-harmonically injection-locked frequency-locked loop and four reflection-type modulators. It can be applied to the performance of various modulation methods due to its high modulation quality and wide bandwidth. Due to the low phase noise and quadrature error of the quadrature frequency-locked loop, the modulation scheme can reach up to 128 QAM. The measured 128-QAM EVM is within 3%. With a symbol rate of 3 GB/s, the measured 16-QAM is within 6%. The overall DC power number is 36.9mW. The proposed 2n-QAM IQ modulator demonstrates good performance and it can be further used in advanced millimeter-wave transmitters. | en_US |