| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 李健民 | zh_TW |
| DC.creator | Jian-Min Li | en_US |
| dc.date.accessioned | 2020-8-20T07:39:07Z | |
| dc.date.available | 2020-8-20T07:39:07Z | |
| dc.date.issued | 2020 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=107521126 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 氮化鎵高電子遷移率電晶體由於其優異的高崩潰電場和高電子飽和速度等特性，在射頻功率放大器之應用具有極大潛力。為應用於毫米波頻段，氮化鎵高電子遷移率電晶體之閘極長度必須縮小至0.2微米或以下。通常此類元件是以電子束微影技術製作，本論文研究則以低生產成本的I-line光學微影技術來製作元件，透過蝕刻回填方式，突破光學微影的極限，達到閘極微縮的效果。
本研究製作之次微米高電子遷移率電晶體，其閘極微縮是利用鈍化層開洞後進行回填的密合現象，再透過電漿非等向性的蝕刻，達到閘極微縮的效果，此製程形成之T型閘極頭部有鈍化層支撐，故可大幅提升製程良率。經過多次製程改良，依序調整曝光劑量與修改光罩尺寸，將曝光關鍵尺寸從0.7μm縮小至0.26μm，並利用氧化鋁的高蝕刻選擇比的材料特性，保持蝕刻垂直度，經過蝕刻回填製程後，最終閘極線寬逐漸從0.27μm微縮至93 nm，達到奈米級的尺寸。
本論文以蝕刻回填的方式製作出閘極線寬為0.27μm的氮化鎵高電子遷移率電晶體，元件之直流轉導最大值(gm,max)為439mS/mm；高頻小訊號特性fT=44GHz，fmax=71GHz，其特性與國際使用電子束微影的研究團隊相比，在相同閘極線寬下，可以有相當的表現，顯示出以光學微影製作小線寬閘極在市場上的價值。 | zh_TW |
| dc.description.abstract | GaN-based high electron mobility transistors (HEMTs) offer great potential in applications such as millimeter-wave power amplifiers due to its excellent high breakdown electric field and high electron saturation velocity. In order to achieve the required device performance in the mm-wave frequency band, the gate length must be scaled down to 0.2 μm or less. Usually, such a small gate footprint is achieved by using electron beam lithography (EBL). In this work, we have demonstrated a cost-effective way to fabricate sub-200 nm T-gate by using I-line optical lithography through etching and backfilling method and further pushed the limit of optical lithography.
The T-gate process consists of depositing a SixNy layer by PECVD followed by defining and opening a window by i-line stepper and ICP etching. The window is subsequently filled by the second layer of SixNy, leading a “U”-shaped surface morphology due to the conformal deposition. The gate footprint is then defined by anisotropic etching to the bottom region of the “U” shaped area followed by the deposition of Ni/Au metal stack. The exposure dose and mask modification are adjusted through several process modifications. The critical exposure size is reduced from 0.7 μm to 0.26 μm, and the high etching selectivity of aluminum oxide is used to maintain the verticality of the etching. The gate length is scaled down from 0.27 μm to 93 nm after etching the backfilled SixNy.
Furthermore, the fabricated devices exhibit excellent DC and RF characteristics. The maximum DC transconductance (gm,max) of 439 mS/mm, small-signal current gain cut-off frequency (fT) of 44 GHz and power gain cutoff frequency (fmax) of 71 GHz are achieved on a device with 0.27 μm gate length. This excellent DC and RF performance is comparable to those of the devices fabricated by using EBL. Therefore, the use of low-cost low-resistivity silicon substrate (LR-Si) and electron beam lithography-free process may help to realize cost-effective RF-GaN HEMTs for next-generation mm-wave applications. | en_US |
| DC.subject | 氮化鎵 | zh_TW |
| DC.subject | 高電子遷移率電晶體 | zh_TW |
| DC.subject | 毫米波 | zh_TW |
| DC.subject | 光學微影 | zh_TW |
| DC.subject | GaN | en_US |
| DC.subject | HEMT | en_US |
| DC.subject | mm-wave | en_US |
| DC.subject | I-line | en_US |
| DC.title | 毫米波氮化鎵高電子遷移率電晶體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Fabrication of Millimeter Wave GaN-Based High Electron Mobility Transistors | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |