| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系 | zh_TW |
| DC.creator | 朱紹誠 | zh_TW |
| DC.creator | Shao-Cheng Chu | en_US |
| dc.date.accessioned | 2021-7-21T07:39:07Z | |
| dc.date.available | 2021-7-21T07:39:07Z | |
| dc.date.issued | 2021 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=107523026 | |
| dc.contributor.department | 通訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 隨著水下技術的快術發展及水下活動的日趨頻繁，水下聲波無線通訊益漸重要。然而，聲波在水下環境所遭遇之能量損耗、多重路徑衰退、頻率和相位擴展現象頗為嚴重，深深影響通訊品質。而北約組織所提出之水下通訊協議—JANUS，對推進水聲通訊建立統一標準。JANUS 的主要作用是使當今的聲學系統相互同步。通過定義一個通用頻率（11.5 kHz）來實現這一點，所有系統都可以通過該頻率宣布它們的存在。一旦兩個系統通過 JANUS 建立聯繫，它們就可以決定切換到不同的頻率或協議，以提供更高的數據速率或傳輸更遠的距離。
本篇論文主要目的為依據北約JANUS水下通訊協議的標準，實現其基頻處理系統，並搭配實驗室現有的FPGA開發環境，利用硬體資源將軟體所模擬之過程在硬體上真實呈現。軟體介面部分，使用MATLAB控制SMIMS Engine IC對FPGA板下達傳送與接收訊號之指令。硬體程式方面是使用Xilinx ISE撰寫Verilog HDL，並用ModelSim驗證整個收發機模組之間的系統整合之時序，再燒入到FPGA進行硬體實測。 | zh_TW |
| dc.description.abstract | With the rapid development of underwater technology and the increasing frequency of underwater activities, underwater acoustic wireless communication has become increasingly important. However, the energy loss, multipath fading, frequency and phase expansion phenomena encountered by sound waves in the underwater environment are quite serious, which deeply affects the quality of communication. The underwater communication protocol proposed by NATO, JANUS, establishes a unified standard for the advancement of underwater acoustic communication. The main role of JANUS is to synchronize today′s acoustic systems with each other. This is achieved by defining a universal frequency (11.5 kHz) through which all systems can announce their existence. Once the two systems establish contact through JANUS, they can decide to switch to a different frequency or protocol to provide a higher data rate or transmit a longer distance.
The main purpose of this paper is to implement its baseband processing system based on the NATO JANUS underwater communication protocol standard, and to match the existing FPGA development environment in the laboratory to use hardware resources to realistically present the process simulated by the software on the hardware. In the software interface part, use MATLAB to control SMIMS Engine IC to send and receive signals to the FPGA board. In terms of hardware programming, Xilinx ISE is used to write Verilog HDL, and ModelSim is used to verify the timing of the system integration between the entire transceiver module, and then burned into the FPGA for hardware testing. | en_US |
| DC.subject | 水下通訊國際標準 | zh_TW |
| DC.subject | 跳頻通訊技術 | zh_TW |
| DC.subject | 收發機 | zh_TW |
| DC.subject | 軟體定義無線電 | zh_TW |
| DC.subject | NATO Underwater Communicationl Standard | en_US |
| DC.subject | Frequency Hopping Communication Technology | en_US |
| DC.subject | Transceiver | en_US |
| DC.subject | Software-Defined Radio | en_US |
| DC.title | 以軟體定義無線電平台設計實現北約組織水下通訊標準收發機 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Implementation of NATO Standard Underwater Communication Transceiver with SDR Platform | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |