| dc.description.abstract | As the technology scaling continues, it is getting more challenging to improve the CMOS power performance by reducing the supply voltage and threshold voltage without prohibitively increasing its leakage power. Moreover, continued scaling of the metal interconnection geometry increases wire resistance which degrades the circuit performance in advanced technology nodes. Cryo-CMOS has emerged as a highly promising solution to improve performance and power efficiency by operating the devices at ultra-low temperatures. Therefore, the thesis explores the performance of SRAM at lower temperatures using TCAD Mix-Mode simulations coupled with the interconnect π-3 model.
This thesis analyzes the read stability, write stability, and speed for 6T and 4T SRAM cells at 300 K and 77 K. Compared to 6T SRAM cell at 300K, 4T SRAM cell at 77K shows 20.3% cell area reduction, 44% reduction in read access time, 46% improvement in write time, 2.3× improvement in write stability, and 53% reduction in energy-delay product (EDP).
The thesis also explores the design methodology of SRAM cell with transistor-level monolithic 3D integration. In transistor-level M3D design, p-type and n-type transistors are fabricated on different layers, which can be optimized separately. The 3D integration reduces the SRAM cell area and reduces the interconnect lengths, which is beneficial for lowering wire routing resistance and capacitance. Compared to the 1-tier 6T SRAM cell at 300K, the monolithic 2-tier 4T SRAM cell shows 62% improvements in read access time, 69% improvements in time to write, and 77% improvements in EDP at 77K. The energy- and areaefficiency of 2-tier 4T SRAM cell enables intelligent functionalities for the energy-constrained edge computing devices. | en_US |