| dc.description.abstract | In order to reach positive VTH in basic tri-gate devices, it is necessary to design nano-level fin-width (WFin) to effectively control the channel to achieve enhancement mode operation, and requires nano-level exposure accuracy. In this work, a normally-off Recessed tri-gate MIS-FET is fabricated and characterized. The Recessed tri-gate MIS-FET in this work is fabricated by micro-level trenches, which are used to define the fin-shaped channel and improve the gate control capability. Even with a micrometer trench width (WTrench), as long as the AlGaN barrier recessed completely under the gate metal, a normally-off recessed tri-gate GaN MIS-FET is achieved. For comparison, standard Recessed planar MIS-FETs were also fabricated using the same process flow on the same chip.
In terms of devices processing, two different device isolation methods, mesa isolation and ion implantation, are used for fabrication. After device are isolated by Ar-ion implantation and are etched trenches by ICP, the recessed surface is cleaned by a diluted BOE, HCl solution, and TMAH treatment before a 20 nm Al2O3 deposition by ALD. Finally, the finished Recessed tri-gate MIS-FET has a WTrench of 1.2 μm, and WFin of 0.8 μm. In I-V measurement, gm,max, ID,max, S.S., RON, and leakage current at off state of Recessed tri-gate MIS-FETs are better than Recessed planar MIS-FETs, which presents the advantages of tri-gate structure. Recessed tri-gate MIS-FET demonstrates a high threshold voltage of 2.5 V, a high drain current of 1121 mA/mm, and an on/off current ratio of 2×10^8. Besides, the devices show a low I-V hysteresis. A hysteresis effect in device I-V characteristics is used to estimate the interface state density(Dit), which is similar to the conductance extraction result in C-V measurements. That is, the device is cleaned by a diluted BOE, HCl solution, and TMAH treatment can improve the interface state density. The C-V measurement was carried out and the Dit distribution at different energy levels was about 4×10^12 eV-1cm-2. All experimental results confirm of combining micro scale trenches to form tri-gate structures and gate recess design can achieve high performance normally-off GaN transistors. | en_US |