| dc.description.abstract | With the development of Moore′s Law, the semiconductor technology allows more transistors in the chip. The computing power of the chip has been greatly improved, so the processing and transmission of data has increased. High-speed serial link becomes the mainstream of the transmission interface and gradually replaces the traditional parallel communication. For example: PCI-Express, USB, SATA, HDMI, DisplayPort and Ethernet, etc. As the data rate increases, the influence of inter-symbol interference (ISI) becomes serious, and the time tolerance interval of the circuit becomes small. Consequently, bit error rate (BER) and jitter tolerance (JTOL) are degraded. How to maintain jitter tolerance and reduce the bit error rate is an issue that must be overcome.
This thesis presents a 16 Gbps half-rate clock and data recovery with data decision compensation technique which takes the PCIe 4.0 specification as a reference material. The proposed decision controller operates the output signal generated by the multi-level bang-bang phase detector (ML BBPD) to obtain the phase error between the data and the recovered clock. Selecting clocks of different phases to sample the data can avoid sampling near the transition edge of the data which improves jitter tolerance and reduces bit error rates. According to whether the phase error is greater than 0.5 UI, the decision controller decides whether the UP and DN signal of the swapping bang-bang phase detector (SBBPD) should be exchanged. Therefore, when the phase error is greater than 0.5 UI, the loop can still be tracked in the correct direction. This technique not only increase the phase error tolerance of the phase detector from 0.5 UI to 1.0 UI, but also exceed the high-frequency jitter tolerance limit of the traditional CDR which is only 0.5 UI. In this thesis, we used TSMC 40 nm (TN40G) 1P10M CMOS process with 0.9 V supply voltage to fabricate the chip and the input data is PRBS7 16 Gbps NRZ signal. In the post-layout simulation, high-frequency jitter tolerance compared to conventional bang-bang CDR is improved by 100 %. At 8 GHz, the measured jitter of the recovered clock is 9.11 pspp and 1.28 psrms, and the power consumption is 47.88 mW. The chip area is 0.998 mm2 and the core area is 0.078 mm2. | en_US |