| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林郁芊 | zh_TW |
| DC.creator | Yu-Cian Lin | en_US |
| dc.date.accessioned | 2022-9-21T07:39:07Z | |
| dc.date.available | 2022-9-21T07:39:07Z | |
| dc.date.issued | 2022 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=108521039 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文提出一個自適應時序及脈波寬度校正技術的次諧波注入式鎖相迴路，且具有多操作頻率的特色，可操作頻率範圍為1.2 GHz – 2.4 GHz，次諧波注入式鎖相迴路具有抑制振盪器產生之高頻相位雜訊的特色，且利用自適應時序及脈波校正的技巧，於不同操作頻率之下仍可固定注入的脈波強度，確保注入式迴路具有相同的相位雜訊抑制效果。注入式鎖相迴路的架構有許多問題可以討論，其影響最為明顯的為注入時序和注入脈波寬度，這些問題會嚴重影響注入式鎖相迴路的操作效能，除了劣化輸出時脈抖動(Jitter)與參考突波(Reference Spur)之外，甚至影響迴路的穩定，因此注入時序校正技術扮演著很重要的角色，需十分重視其中的設計。本研究採用振盪器相位之間固定之相差，自適應調整最佳的注入強度，也透過此技術使此電路可活運用在不同頻率，進一步提升應用範圍。
電路設計與佈局採用90 nm CMOS製程來實現。在供應電壓為1 V的條件下，輸出頻率可以操作於1.2 GHz – 2.4 GHz。完成注入時序與脈波寬度校正後，次諧波注入式鎖相迴路的參考突波與主頻率的能量差為-34 dBc，輸出相位雜訊在1MHz的情況下為-110.7 dBc/Hz，整個電路的功率消耗在最高頻率2.4 GHz為4.04 mW，核心電路面積為0.102 mm2，晶片面積為1.49 mm2。 | zh_TW |
| dc.description.abstract | This thesis proposes a sub-harmonically injection locked phase-locked loop with self-calibrated injection timing and pulsewidth technique, The operating frequency range is 1.2 GHz – 2.4 GHz. The sub-harmonically injection locked phase-locked loop has the ability to suppress the high frequency noise generated by the oscillator. Through the use of self-calibrated injection timing and pulsewidth technique, the injected pulse intensity can still be fixed under different operating frequencies. According to the technique, it ensures that the injection loop has the same phase noise suppression effect. There are many problems in the architecture of the injection locked phase-locked loop that can be discussed. The most obvious impact is the injection timing and the injection pulsewidth. These problems will seriously affect the operation performance of the injection locked phase-locked loop. In addition to deteriorating the output clock jitter and reference spur, it also affects the stability of the loop. Therefore, the technology of injection timing correction needs to be paid high attention to. In this study, the fixed phase difference between the oscillator phases is used to adaptively adjust the optimal injection strength. This technology also enables the circuit to be used in different operation frequency to further enhance the applicability.
This work is fabricated in 90 nm CMOS process, the output frequency range of the sub-harmonically injection phase-locked loop is 1.2 GHz - 2.4 GHz under the condition that the supply voltage is 1V. The measured phase noise at 1 MHz offset -110.7 dBc/Hz, The measured reference spur is -34 dBc. The power consumption of the circuit is 4.04 mW at the highest frequency of 2.4 GHz. | en_US |
| DC.subject | 注入式鎖相迴路 | zh_TW |
| DC.subject | 自我校正注入時序 | zh_TW |
| DC.subject | Sub-harmonically injection-locked PLL | en_US |
| DC.subject | self-calibrated injection timing | en_US |
| DC.title | 具自我校正注入時序與脈波寬度技術之多頻率次諧波注入式鎖相迴路 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A Multiple Frequency Sub-harmonically Injection Locked Phase Locked Loop with Self-Calibrated Injection Timing and Pulsewidth Technique | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |