| dc.description.abstract | With the development and popularization of today′s technology, people′s dependence on the network is getting higher, and the demand for transmission speed of devices or equipment is also increasing. In high-speed Ethernet transmission systems, such as 2.5GBASE-T or 5GBASE-T system, eliminating echo interference is an important issue. Traditional echo cancellers are often implemented with digital circuits, and the echo channel response can be divided into several segments, the maximum value of echo channel response falls at the forefront. If an analog echo canceller is added to the traditional digital echo canceller, the maximum value can be eliminated before entering the digital circuit to achieve the effect of reducing the number of bits in the subsequent digital circuit. In this analog echo canceller, an analog algorithm circuit is required to provide the coefficients of the analog filter.
According to the IEEE 802.3bz™-2016 specification standard, this thesis presents a design of an analog Least Mean Square algorithm circuit, which is composed of into two parts: a multiplier circuit and an integrator circuit. The former uses the architecture of Gilbert cell as the multiplier of the algorithm to realize the multiplication function of the analog coefficient input and the analog data input, and adjust the input swing based on the system environment, while improving the input swing, it can also have a good the performance of linearity; the latter uses a switched-capacitor integrator, which realizes the addition function of the algorithm and the function of coefficient storage. Adjusting the gain of the multiplier and the ratio of the feedback capacitor of the integrator to integral capacitor of the integrator can determine the step size of the algorithm circuit, and realize this design with a fully differential architecture can reduce the influence of process deviation, voltage deviation and temperature on the system, so that this design has better performance of error value.
This circuits are designed in TSMC 45 nm CMOS LOGIC General Purpose Superb (40G) ELK Cu 1P10M 0.9/2.5V, the chip area is 0.25mm2 (including I/O PAD), the supply voltage is 2.5V and 0.9V, the operating frequency is 200MHz, and the power consumption of the core circuit is 3.21mW. Finally, the average error of the whole chip is -47.31dB. | en_US |