| dc.description.abstract | In recent years, with the evolution and development of manufacturing processes, the demand for high-speed analog circuits is increasing. For example: high-speed analog-to-digital converters (ADC), digital-to-analog converters (DAC), high-resolution image transmission equipment...etc. Among them, high-bandwidth, high-slew rate operational amplifiers play a very important role. This paper proposes three architectures. The first architecture is a high-power linear regulator implemented using a GaN process, which can stably convert 100V to 5.5V to provide a stable power supply voltage to the other two architectures. The other two architectures are analog circuits designed to amplify the output signal of a high-speed digital-to-analog converter (DAC) to drive high loads. They are an operational amplifier with high bandwidth, high slew rate, and low output impedance. The architecture is mainly divided into two types: The first is a typical voltage feedback complementary two-stage amplifier (G1) with slew rate compensation drive circuit, its open loop gain can reach 69dB, unity gain bandwidth 183M Hz, its static power The power consumption can reach 6.3mW. The other is a current feedback transimpedance amplifier (G2) with high bandwidth, high slew rate, and low output impedance. Its open-loop gain can reach 50dB. The slew rate is at the output peak-to-front value VPP=2.5V and load 0.9nF//50ohm is 582V/μs, unity gain bandwidth is 325M Hz, its output impedance can reach 0.1ohm (@10 M Hz), and static power consumption is 1.25W. The architecture proposed in this paper is implemented by an integrated circuit, used through a 0.18um CMOS process, with a single supply voltage of 5.5V, a load impedance of 0.9nF//50ohm, and the total harmonic distortion (THD) when the test signal frequency is 10M Hz. Is 2.4%. 8% at 30M Hz. | en_US |