| dc.description.abstract | The data rate of serial transmission systems keeps growing as technology progresses. In addition, bandwidth design becomes more difficult. The 4-level PAM-4 pulse amplitude modulation technology can be used to reduce the difficulty of the bandwidth design. The required bandwidth is halved compared to non-return-to-zero transmissions. Parallel transmission has been replaced at the same time by serial transmission. For instance, serial transmission system interfaces are used by USB, SATA, PCI-E, DisplayPort, and other devices. By reference to the Common Electrical Interface-28G-Very Short Reach (CEI-28G-VSR) specification, a data and clock recovery circuit is implemented in this article.
The CEI-28G-VSR is used in this research to create a data and clock recovery circuit employing 4-level PAM-4 pulse amplitude modulation. And, to address the previous literature′s problem of insufficient transition source of the phase detector, a new transition selector with fourth-order pulse amplitude modulation is proposed, so that the data and clock recovery circuit has a higher phase tracking ability, and improving the detection data edge type can effectively reduce the recovered clock jitter. In this thesis, the non-referential edges of the 4-level PAM-4 pulse amplitude modulation are ignored in order to avoid adding extra recovered clock jitter. In this thesis, the overall power consumption is decreased by quarter rate and baud rate sampling. The circuit of this thesis is designed in 40 nm standard CMOS process. The input data is 20 Gbps PAM-4, the recovery clock rate is 2.5 GHz, the supply voltage is 0.9V, the chip area is 1.11 mm2, the core area is 0.135 mm2, the peak-to-peak jitter of the recovery clock is 18.9 ps, and the RMS jitter of the recovery clock is 2.73 ps, with a power consumption of 17.52 mW. | en_US |