dc.description.abstract | In recent years, as the demand of data communication has increased rapidly, high speed serial link interface come out with new specification operating at higher data rate to be in line with the market’s demand. While the data rate increases gradually, the channel bandwidth does not follow up. Since then, the data suffers more inter-symbol-interference (ISI), it is necessary to use equalizer compensate the data for ensuring the quality of received signal. The past assay proposed various types of equalizer to deal with the increasing data rate. However, these methods make the energy efficiency of high-speed serial link system worse. Therefore, we should research for low power techniques rather than high data rate interface.
This thesis proposes a new architecture of equalizer, which is composed by continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). It broadens the time constrain of DFE from one data period to two data period by new compensation method. Since we broaden the time constrain of DFE, we are able to use low power techniques on equalizer. Moreover, this thesis uses adaptive system to converge the weight of both equalizers to obtain correct compensation. This thesis proposes a new adaptive method based on the proposed equalizer, and this allow us to converge boost gain of CTLE and the tap weighting of DFE at the same time with single adaptive system.
The fabricated chip was implemented by TSMC 90 nm (TN90GUTM) 1P9M CMOS process. In post-layout simulation, power supply is 1.0 V, the input data rate is 16 Gbps, the input clock frequency is 8 GHz, and the channel loss is 16 dB. The power consumption of core is 5.40 mW, which includes CTLE consumed 1.78 mW, DFE consumed 1.12 mW, and adaptive system consumed 2.50 mW. In measurement results, the input data rate is 8 Gbps, the input clock frequency is 4 GHz, and the channel loss is 21 dB. The power consumption of core is 4.3 mW, which includes CTLE consumed 1.8 mW, DFE consumed 0.6 mW, and the adaptive system consumed 1.9 mW. The chip area is 1.2 mm2 and the core area is 0.047 mm2. | en_US |