| dc.description.abstract | As circuits operate at higher speeds, designing a clock generator with good performance must account for output jitter, noise, power consumption, and area. Although the LC oscillator has better noise performance, it needs to occupy more area, while the ring oscillator has poor noise performance, but the area is relatively small. In this thesis, a small-area and low-noise phase-locked loop (PLL) is implemented using a ring oscillator combined with a simple technique to suppress phase noise and reference spurs.
In recent years, a common circuit used to reduce phase noise is a sub-sampling phase-locked loop(SSPLL), which effectively reduces phase noise by removing the frequency divider when the loop is locked. However, when the sub-sampling phase detector detects a phase difference between the reference clock and the high-frequency output signal of the voltage-controlled oscillator, periodic disturbances cause serious reference spur problems to the high-frequency output signal. Combining the concept of a sub-sampling PLL with a baud-rate phase detector in a clock and data recovery circuit (CDR), an alternative phase detection method is proposed that can detect the phase difference between two different frequencies. After the loop is locked, the divider in the loop is removed, thus reducing the phase noise. At the same time, the interference caused by the phase detector to the VCO is minimized, and low reference spur, low phase noise and small-area PLL circuits are realized.
This work is fabricated in TSMC 90 nm 1P9M CMOS process, the output frequency is 2.4 GHz when the supply voltage is 1V. The measured phase noise of traditional charge pump PLL(CPPLL) at 1 MHz offset -104 dBc/Hz, the rms jitter is 2.21 ps, and reference spur is -56.5 dBc. The measured phase noise of proposed baud-rate phase detect PLL at 1 MHz offset is reduced to -114 dBc/Hz, the rms jitter is reduced to 1.30 ps, and reference spur is -54.1 dBc. The power consumption of the circuit is 3.77 mW. The die area is 0.080 mm2 and active core area is 0.027 mm2. | en_US |