| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林藝真 | zh_TW |
| DC.creator | Yi-Jhen Lin | en_US |
| dc.date.accessioned | 2024-1-17T07:39:07Z | |
| dc.date.available | 2024-1-17T07:39:07Z | |
| dc.date.issued | 2024 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=109521010 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 為了提高電子產品的操作頻率，且電路操作在準確的頻率時，時脈訊號的能量會被集中在單一頻率，這表示著時脈訊號包含了許多的高次諧波能量。這些高頻訊號對於周邊的電路而言，無疑是形成了電磁干擾( EMI )，並可能導致電路的操作異常，因此電磁波干擾抑制技術，明顯成為電子產品必須解決的根本問題。本論文提出一個應用於SATA-III規格與可控頻率調變曲線的展頻時脈產生器(SSCG)，在不改變展頻調變量與調變頻率的情況下，改變頻率調變曲線，來實現電磁干擾的抑制，並利用高解析度的相位切換除頻器，讓頻率變化的幅度降低，以達到較低的系統抖動表現。
本論文使用TSMC 90 nm CMOS製程實現，電路操作電壓為1.0 V，中心頻率為6 GHz，調變波型之調變頻率為31.25 kHz，向下展頻4166 ppm。展頻機制開啟後，根據頻率調變曲線的變化，電磁干擾抑制量會從24 dB提升到26 dB。整體晶片面積為0.96 mm2，核心電路面積為0.053 mm2，整體電路的功率消耗為24.9 mW，未開啟與開啟展頻模式的方均根抖動分別是0.11 ps 與 0.23 ps，未開啟與開啟展頻模式的峰對峰值抖動分別是1.13 ps 與 1.50 ps。 | zh_TW |
| dc.description.abstract | To enhance the operating frequency of electronic products, when the circuit operates at an accurate frequency, the energy of the clock signal will be concentrated at a single frequency. This indicates that the clock signal contains a significant amount of high-order harmonic energy. For peripheral circuits, these high-frequency signals undoubtedly generate electromagnetic interference (EMI), potentially leading to circuit malfunctions. Therefore, electromagnetic interference suppression techniques have become a fundamental issue that electronic products must address.
This thesis proposes a Spread Spectrum Clock Generator (SSCG) applied to the SATA-III specification with a controllable frequency modulation profile. Without changing the spreading modulation amount and modulation frequency, the paper modifies the frequency modulation curve to achieve EMI suppression. By using a high-resolution phase-switching divider, the magnitude of frequency variation is reduced to achieve lower system jitter performance.
This work is implemented using the TSMC 90 nm CMOS process, operating at a voltage of 1.0 V, with a central frequency of 6 GHz. The modulation frequency of the modulation waveform is 31.25 kHz, and the downward spread is 4166 ppm. When the spreading mechanism is activated, the EMI suppression increases from 24 dB to 26 dB due to changes in the frequency modulation curve. The overall chip area is 0.96 mm2, with a core circuit area of 0.053 mm2. The power consumption of the entire circuit is 24.9 mW. The root mean square (RMS) jitter in both deactivated and activated spread modes is 0.11 ps and 0.23 ps, respectively. The peak-to-peak jitter values in both modes are 1.13 ps and 1.50 ps, respectively. | en_US |
| DC.subject | 展頻時脈產生器 | zh_TW |
| DC.subject | 鎖相迴路 | zh_TW |
| DC.subject | Delta-Sigma調變 | zh_TW |
| DC.subject | 鋸齒波 | zh_TW |
| DC.subject | 可控頻率調變曲線 | zh_TW |
| DC.subject | Spread spectrum clock generator | en_US |
| DC.subject | Phase locked loop | en_US |
| DC.subject | Delta-Sigma modulation | en_US |
| DC.subject | Sawtooth | en_US |
| DC.subject | controllable modulation profile | en_US |
| DC.title | 應用於SATA-III規格之可控頻率調變曲線的展頻時脈產生器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A SATA-III Spread-Spectrum Clock Generator with Controllable Frequency Modulation Profile | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |