| dc.description.abstract | Single-photon Avalanche Diodes (SPADs) are important in many fields of science and industry, such as quantum key distribution, light detection and ranging (LiDAR) for self-driving cars, and also 3D imaging technology, etc. Especially, a very sensitive photon detector is highly demanded in the fiber-based photonic quantum communication. Therefore, we focus on the development of InGaAs-based SPAD for near infrared light detection. However, there are lots of defects during the epitaxy of III-V materials, which will cause serious afterpulsing effect and dark count problems. Since InAlAs exhibits high avalanche probability and hence high single photon detection efficiency (SPDE), we put our focus on the study of InGaAs/InAlAs SPADs.
In this thesis, we present a comprehensive investigation on the InGaAs/InAlAs SPADs with triple multiplication layer. Compared with the previous structure design of dual multiplication layers, the increase in the thickness of the multiplication layer is also expected to reduce the effect of tunneling current and increase the probability of avalanche. However, this design may increase the probability of afterpulsing effect and degrade the timing jitter. Therefore, we propose a novel design in the multiplication layer - an additional charge layer. It can divide the multiplication layer into high electric field and sub-high electric field region, so that the avalanche breakdown region can be restricted within a smaller area.
The figure of merits (FoM) of single photon detector for three mesa-type SPADs with different punch through voltage are studied. Those three SPADs have almost the same breakdown voltage but very different punch through voltage of 9V, 16V and 30V. We also compare FoMs of SPAD for the cases with and without the inclusion of self-differencing circuit.
SPADs were operated by a passively gated mode circuit. Depending on whether or not to use the SD circuit, the operating frequency is set at 9.9 MHz or 10 kHz with the pulse width of 1.5 ns. With reducing the temperature, the dark count rate (DCR) can be effectively suppressed for dual mesa device. It also exhibits higher SPDE of 64 % at 200 K .There is no much difference in the timing jitter and also afterpulsing for all three devices. Besides, we further discuss the impact of incorporation of SD circuit on the device performance. It turns out that the DCR can be greatly suppressed with SD circuit, which improves the SPDE at lower temperature. However, because the DCR is high at room temperature, the detector can be blinded while there are two consecutive avalanche events, which restricts the count rate so as to draw a limit on the SPDE performance at room temperature.
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