dc.description.abstract | The phased array system is used in the front end of the transceiver to adjust the beam direction to achieve beamforming, whether it is a radar system or a fifth-generation mobile communication, the phased array has an irreplaceable position. The phase array is usually composed of a phase shifter and a variable gain amplifier, and then is matched with a power amplifier or a low noise amplifier according to the transmitting or receiving end to achieve an adjustable phase and amplitude. Variable gain amplifiers are key circuit elements in phased arrays. In this paper, a digital phase shifter and a digital variable gain amplifier are respectively proposed to operate in the K band, and implemented using TSMC 0.18-µm CMOS process.
In Chapter 2, we use TSMC 0.18-µm CMOS process to implement a K band five-bit passive phase shifter, 11.25◦, 22.5◦, 45◦, 90◦ phase shifter is an all-pass network architecture using the transmission line reference all-pass network, and the 180◦ phase shifter is implemented using the SPDT architecture. This chip is divided into two versions. From the measurement results of the first version, we found that the model of the MIM capacitor in the TSMC 0.18-µm CMOS process may overestimate the parasitic inductance, so we connected the MIM capacitor in series in the re-simulation. Negative inductance, thereby deducting the parasitic effect of overestimation. Finally, in the second version, the trimmer capacitors were redesigned to correct various parameters. The redesign results showed that the RMS phase error was lower than 4◦ from 20.4 GHz to 31.1 GHz, the return loss was lower than 11.2 dB, insertion loss is less than 17.1 dB in bandwidth, RMS amplitude error is less than 0.5 dB.
In Chapter 3, we use TSMC 0.18-µm CMOS process to implement a K frequency band five-bit variable gain amplifier, and digitally switch the bias voltage to achieve the gain of different states. The circuit consists of five fully differential stacks. The amplifier structure is composed of parallel connection, the input end uses a 1:2 transformer matching, and the output end uses an L-type matching network with a series capacitor and a parallel inductor. This circuit is mainly used in the ISM frequency band (24-24.5 GHz). The simulation results show that the input return loss is greater than 18.62 dB, the output return loss is greater than 11.53 dB, and the gain is greater than 10.56 dB, and the phase change is 37◦. The measurement results show that the peak gain is shifted from 24 GHz to 21.9 GHz, and the input return loss is 13.5 dB in the fully open state, the output return loss is 5 dB, the gain is 5.7 dB, the phase change is 25.7◦, overall Except for the reduction in phase variation, all other data measurements are worse than the simulation, especially the gain and output return loss. When re-simulating, we will bring in the neglected traces, including the traces between the input terminal, the output terminal and the transistor. After bringing in the traces, we will indeed correct the trend of low frequency deviation. In order to make the return loss and gain fit the measurement results, we put a resistor in parallel next to the transformer at the input and a series resistor next to the inductor at the output. After re-simulating the results, the gain peak frequency is 21.8 GHz. When the gain peak frequency is fully open, the input return loss is 13 dB, the output return loss is 5 dB, the gain is 5.7 dB, and the maximum phase change is 30◦. It can be seen that by re-simulating, except for the phase change, which is about 4◦ compared with the measurement, other data are consistent with the measurement results. In addition, according to the present architecture, the phase change is plotted against the frequency, and it is found that there is a large phase change near the gain peak, which is worthy of subsequent discussion and improvement.
In this paper, we implemented a K band digital phase shifter and variable gain amplifier, and concluded that the phase shifter was redesigned to be very close to analog, and the variable gain was re-simulated It can also be fitted and measured later. Using the above experience, we can estimate the parasitic effects of the TSMC 0.18-µm CMOS process in the K band, so that our future circuit simulation can be more accurate. | en_US |