| dc.description.abstract | Among various non-volatile memory technologies, spin-transfer torque magnetic random access memory (STT-MRAM) is a promising memory for advanced technology nodes due to its lower read/write latency, better durability, and data retention. Furthermore, STT-MRAM has been considered as a candidate of in-memory computing (IMC) architecture for data-intensive applications. However, STT-MRAM has the inherent properties of low tunneling magnetoresistance (TMR) and thermal disturbance. Also, the fabrication of the magnetic tunnel junction (MTJ) device induces new defects. Those cause that the testing and yield enhancement are two key challenges for the volume production of STT-MRAMs. In the first part of this thesis, we propose a trimming technique for STT-MRAM IMC memories. The trimming technique uses the lookup table to store the expected error number with respect to different trimming resistances in terms of simulation probability distribution in the design phase. In the production test phase, a trimming test is executed for the boundary trimming resistance and the fail bit counts can be obtained. Then, we can select an appropriate reference resistance by comparing the fail bit counts with the expected error number in the lookup table. Since only the boundary trimming resistance is used for the trimming test, the trimming test complexity is O(1). In comparison with existing binary search approach, the proposed trimming technique can achieve about 45.77% and 99.99% test time reduction in memory mode and computing mode, respectively. Furthermore, compared to the scenario without trimming, it can also enhance variation tolerance by up to 8%. In the second part of this thesis, we propose a design-for-testability(DFT)-enhanced test scheme for STT-MRAMs. In a test algorithm, the read current of a read operation can be adjusted through DFT circuits to extend the detectable range of defect size such that the test quality is improved. Simulation results show that a 17.5N test algorithm with adjustable read current can cover about 19 times of defect size than conventional test algorithm without read current adjusting. A test complexity and test quality optimization approach is proposed to reduce the test complexity. The 17.5N test algorithm can be reduced to 7N and achieve about 17 times of defect size coverage. Compared to traditional algorithms, the proposed algorithm achieves at least 2.6 times higher test quality at similar complexity levels. In the third part of this thesis, we propose a programmable built-in self-test (PBIST) scheme for STT-MRAMs. The PBIST scheme can support the trimming test, production test, and DFTenhanced test. A novel instruction set is proposed to reduce the size of microcode of the PBIST by taking advantage of the symmetric characteristics of March tests. In comparison with existing works, the proposed instruction set can realize march and non-march tests, such as March Y, March C+, March SS, Galloping, Walking, and Butterfly, using only about 52.7% microcode bits. We design a PBIST for 256Kx256-bit MRAM using TSMC 40nm CMOS standard cells to support the trimming test for 6-bit trimming resolution. The area cost of the PBIST is about 14654μm2 at the operation frequency of 2GHz. | en_US |