| dc.description.abstract | Due to the flourishing development of the Internet of Things (IoT), various electronic products in the market are utilizing One-Time Programmable (OTP) memory for persistent data and security code storage. The stored data in OTP memory cannot be altered after programming. Research indicates a significant increase in the number of bits used in various products over the past decade, leading to an increased layout area for OTP memory arrays in chip design, prompting the need for in-depth investigation into area design issues.
In this thesis, a mechanism involving the breakdown of fuses is employed. During programming, a high current is generated by applying pressure, flowing through the fuse location. Electromigration at the fuse location induces a configuration change, transforming the fuse from a low resistance value (~50 Ω) to a high resistance value (3K~10 GΩ), achieving the programming functionality. Traditional fuses used Poly-Fuse, but currently, Metal-Fuse is preferred, utilizing a metal layer for 3D integration stacked above MOSFET to reduce layout area.
As fuse breakdown primarily depends on the force of electromigration, theoretically, designing a smaller cross-sectional area for the fuse reduces the required voltage, current, and programming time, demonstrating scalability with technology scaling. Existing eFuse single programmable memory cells typically use only one fuse to form a memory cell, usually adopting a 1T-1F configuration, meaning one memory cell stores one bit. This project proposes an innovative 1T-nF eFuse OTP NVM architecture, utilizing different metal layers as fuses. During programming, a target metal layer is specified to carry a high current. Compared to the traditional 1T-1F structure, the 1T-nF architecture in this study allows one memory cell to store n bits, significantly reducing the layout area.
The bit cell area of the designed eFuse OTP NVM in this research is only 0.447µm^2, with a programming voltage of 1.8V, much lower than the 4-5V required for anti-fuse breakdown. It achieves a reading speed of 15ns with peripheral circuits and undergoes interference testing, repeated fuse reading of 〖10〗^12 times, and data retention reliability testing at 200°C for a month without observing changes in the metal fuse resistance state. This design effectively addresses the issue of the excessive footprint of current eFuse OTP NVM arrays. | en_US |