dc.description.abstract | The Q band in the millimeter-wave frequency range (33--50.5 GHz) has been widely applied in recent years due to its larger bandwidth, higher transmission speed, and shorter latency. Q band finds applications in meteorological radar, 5G mobile communications, and emerging satellite internet. Regardless of these applications, phased arrays play an indispensable role in the transmitter-receiver architecture, and phase shifters are crucial components within phased arrays. By providing adjustable phase differences to the antennas in the phased array, phase shifters enable the manipulation of the direction of transmission and reception.
In Chapter 2, we designed the circuit using the TSMC 90-nm CMOS process, with a center frequency of 35 GHz. A five-stage digital phase shifter was implemented to achieve a five-bit passive phase shifter in the Ka band. The phase shifters 11.25°、22.5°、45° and 90° , were all implemented using a transmission line-based quasi-all-pass network structure. The 180° phase shifter was realized using a single-pole, double-throw (SPDT) switch pair. Based on the measurement results, the root mean square phase error is within 4° with a bandwidth of 32 to 42.7 GHz, which corresponds to a bandwidth of 28.64\% ; the return loss is greater than 10.8 dB within the bandwidth, and the insertion loss is less than 15 dB. The amplitude error is within ±0.7 dB.
In Chapter 3, we designed the circuit using the TSMC 90-nm CMOS process, with a center frequency of 35 GHz. A five-stage digital phase shifter was combined to form a wideband five-bit passive phase shifter in the Ka band. The phase shifters, 11.25°, 22.5°, 45°, and 90°, were all implemented using a transmission line-based quasi-all-pass network structure. To increase the bandwidth, the 90° phase shifter was realized by combining two transmission line-based quasi-all-pass networks with center frequencies offset. The 180° phase shifter was implemented using an SPDT switch pair. Based on the measurement results, the root mean square phase error is within 4° with a bandwidth of 29 to 45.1 GHz, which corresponds to a bandwidth of 43.45\% ; the return loss is greater than 10.4 dB within the bandwidth, and the insertion loss is less than 17.9 dB. The amplitude error is within ±0.55 dB.
In Chapter 4, we designed the circuit using the TSMC 90-nm CMOS process, with a center frequency of 38 GHz. To reduce the circuit loss, we replaced the three-stage digital phase shifter with a single-stage analog phase shifter and combined it with the 45° and 90° digital phase shifters to form a five-bit passive phase shifter in the Q band. To increase the bandwidth, the 45° and 90° phase shifters were implemented by combining two transmission line-based quasi-all-pass networks with center frequencies offset. The analog phase shifter was implemented using MOS varactor to achieve variable capacitance and combined with a digital potentiometer (DPOT) controlled digitally, replacing the 5.625°, 11.25°, and 22.5° digital phase shifters. The measurement results showed that the root-mean-square phase error was larger than the simulation results. The root mean square phase error is within 4° with a bandwidth of 36 to 48.5 GHz, which corresponds to a bandwidth of 29.58\% ; the return loss is greater than 13.5 dB within the bandwidth, and the insertion loss is less than 18.3 dB. The amplitude error is within ±0.75 dB. The root mean square phase error is within 5° with a bandwidth of 27.2 to 51.3 GHz, which corresponds to a bandwidth of 61.4\% ; the return loss is greater than 13.5 dB within the bandwidth, and the insertion loss is less than 18.3 dB. The amplitude error is within ±1.1 dB.
In this thesis, we successfully implemented a CMOS phase shifter in the Q band using a transmission line-based quasi-all-pass network. By combining two transmission line-based quasi-all-pass networks with offset center frequencies to form a single-stage phase shifter, we achieved improved circuit bandwidth. By replacing the three-stage digital phase shifter with a single-stage analog phase shifter, we reduced circuit loss and achieved 180° phase shift resolution and six bits (5.625°) of phase resolution. | en_US |