| dc.description.abstract | This thesis utilizes the 0.18-µm CMOS 1P6M process provided by Taiwan Semiconductor Manufacturing Company (tsmc™). It investigates two distinct power combining techniques for power amplifiers operating within the n77 to n79 frequency bands. The analysis centers on filter and transformer topologies, delving into the loss and constituent conditions of the matching network to optimize its configuration, thereby facilitating the design of power amplifiers.
The first proposed amplifier is a single-stage current combining power amplifier tailored for the n79 frequency band. To mitigate the low impedance challenges inherent in the current combining structure, appropriate transistor sizing is employed to optimize the transistor′s output load impedance, aligning it more closely with the impedance point of the output match. This approach makes the design and fabrication of the matching network easier. Ultimately, within the frequency range of 4.4 - 5.0 GHz, the achieved performance metrics include an optimal gain of 12 dB, a saturation output power of 27.1 dBm, and a peak power-added efficiency of 16.5%. The chip area measures 3.51 (2.02 × 1.73) mm².
The subsequent proposed amplifier targets the n77 to n79 frequency bands, employing a two-to-one transformer matching approach. Through the utilization of specific gate bias and transistor sizes, the optimization of the transistor′s output load impedance is aimed at establishing a defined ratio with the output impedance, thereby achieving the intended two-to-one transformer matching. Additionally, a specialized circuit layout is implemented to reduce the parasitic capacitance associated with the transformer matching, effectively compacting the circuit area of the matching network. Ultimately, within the frequency range of 3.6 - 5.6 GHz, this configuration attains an optimal gain of 10 dB, a saturation output power of 26 dBm, and the highest power-added efficiency of 19.4%. The chip area measures 2.22 (2.13 × 1.04) mm². | en_US |