| DC 欄位 |
值 |
語言 |
| DC.contributor | 資訊工程學系 | zh_TW |
| DC.creator | 吳定濂 | zh_TW |
| DC.creator | Ding-Lian Wu | en_US |
| dc.date.accessioned | 2023-7-28T07:39:07Z | |
| dc.date.available | 2023-7-28T07:39:07Z | |
| dc.date.issued | 2023 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=110522047 | |
| dc.contributor.department | 資訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 衛星與可重組化計算相結合，為系統提供更高的靈活性和適應性。然而，缺乏安全的更新途徑可能導致惡意硬體木馬的植入或攻擊者竊取機密硬體設計。現有的安全更新機制無法有效阻擋惡意重組或讀回攻擊，使得可重組介面面臨重大威脅。因此，我們的設計利用可信執行環境（TEE）來構建安全的 FPGA 動態部分可重組方案，有效保護 FPGA 免受攻擊者侵害。最後，我們在 Xilinx Zynq UltraScale+ MPSoC 設備上實現了該方案，並評估了其時間和空間開銷。 | zh_TW |
| dc.description.abstract | Satellites combined with reconfigurable computing offer higher flexibility and adaptability to systems. However, the lack of a secure update path can lead to the implantation of malicious hardware Trojans or the theft of confidential hardware designs by attackers. Existing security update mechanisms are unable to effectively block malicious reconfiguration or readback attacks, exposing the reconfiguration interface to significant threats. Therefore, our design utilizes a trusted execution environment (TEE) to construct a secure FPGA dynamic partial reconfiguration scheme that effectively protects the FPGA from attackers. Finally, we implemented the scheme on the Xilinx Zynq UltraScale+ MPSoC device to evaluate its time and space overhead. | en_US |
| DC.subject | FPGA 更新 | zh_TW |
| DC.subject | 動態部分可重組 | zh_TW |
| DC.subject | 可重組化計算 | zh_TW |
| DC.subject | 可信執行環境 | zh_TW |
| DC.subject | ARM TrustZone | zh_TW |
| DC.subject | FPGA Update | en_US |
| DC.subject | Dynamic Partial Reconfiguration | en_US |
| DC.subject | Reconfigurable Computing | en_US |
| DC.subject | Trusted Execution Environment | en_US |
| DC.subject | ARM TrustZone | en_US |
| DC.title | 衛星上可重組化計算之安全FPGA動態部分可重組架構 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Secure FPGA Dynamic Partial Reconfiguration Architecture for Reconfigurable Computing on Satellites | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |