| DC 欄位 |
值 |
語言 |
| DC.contributor | 通訊工程學系 | zh_TW |
| DC.creator | 劉亦軒 | zh_TW |
| DC.creator | Yi-Hsuan Liu | en_US |
| dc.date.accessioned | 2023-12-28T07:39:07Z | |
| dc.date.available | 2023-12-28T07:39:07Z | |
| dc.date.issued | 2023 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=110523040 | |
| dc.contributor.department | 通訊工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 第二代數位衛星廣播(DVB-S2(X))在現代通訊領域扮演著重要角色，在通道編碼方面，使用BCH碼作為外碼，LDPC碼作為內碼，用兩種錯誤更正碼組合，以提供更好的糾錯與更正能力。
本論文研究內容為解決硬體解碼效能不如軟體解碼效能之問題，提升LDPC解碼器的資料吞吐率，並加入DVB-S2X Short Frame的規格，使原先只支援DVB-S2規格的LDPC解碼器可支援DVB-S2(X)規格，再以Xilinx的RFSoC ZCU111實現與驗證DVB-S2(X)規格的LDPC解碼器。解碼使用的演算法為硬體複雜度較低的Min-Sum演算法。由於DVB-S2(X)之LDPC校驗矩陣可排列成為QC(Quasi-Cyclic)-LDPC校驗矩陣，故設計上使用適用於QC-LDPC且平行處理資料的硬體架構。此外，LDPC解碼器可以透過參數及控制訊號的配合進行對應的解碼模式。 | zh_TW |
| dc.description.abstract | The second generation of digital satellite broadcasting (DVB-S2(X)) plays a crucial role in the modern communication domain. In terms of channel coding, it utilizes BCH code as the outer code and LDPC code as the inner code, combining two error correction codes to provide enhanced error detection and correction capabilities.
The research focus of this thesis is to address the issue of hardware decoding performance lagging behind software decoding, aiming to enhance the data throughput of the LDPC decoder. Additionally, the DVB-S2X Short Frame specification is incorporated, enabling the LDPC decoder that originally supported only DVB-S2 specifications to accommodate DVB-S2(X) specifications. The implementation and verification of the DVB-S2(X) LDPC decoder are carried out using the Xilinx RFSoC ZCU111. The decoding algorithm employed is the Min-Sum algorithm with lower hardware complexity. Given that the LDPC parity-check matrix of DVB-S2(X) can be rearranged into a Quasi-Cyclic (QC) LDPC parity-check matrix, the hardware architecture is designed to be suitable for QC-LDPC and parallel data processing. Moreover, the LDPC decoder can adapt its decoding mode through the coordination of parameters and control signals. | en_US |
| DC.subject | 低密度奇偶檢查碼 | zh_TW |
| DC.subject | QC-LDPC | zh_TW |
| DC.subject | Min-Sum演算法 | zh_TW |
| DC.subject | LDPC解碼器 | zh_TW |
| DC.subject | FPGA | zh_TW |
| DC.subject | ZCU111 | zh_TW |
| DC.subject | 第二代數位衛星廣播 | zh_TW |
| DC.title | DVB-S2(X) LDPC高資料率解碼器 之FPGA設計、實現與驗證 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design, Implementation and Verification of High Throughput DVB-S2(X) LDPC Decoder with FPGA | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |