| dc.description.abstract | In this thesis, a novel timing and data recovery algorithm for high-speed serial link is proposed. Instead of using the traditional PLL, we use the phase picking architecture. In our design, a 5X oversampling using multi-phase clocks are used to obtain the data information. And our purpose is to find the data transition position and pick the optimum phase for data sampling according to such information.
The transition point may move due to static phase error or jitters (dynamic phase error due to noise). These non-ideal effects cause the reduction of SNR and timing margin. So, the system should detect the phase errors and output a recovery clock to track it.
First, a majority voter chain is applied to enhance the data reliability. Then the transition position of each bit can be detected by XOR. The transition information are accumulated in the confidence counter and the machine will decide that whether the sampling phase should change. By such recovery mechanism, the sampling phase is fixed at the central point of data. Finally, according to the phase selected, three sample values are processed by a majority voter to obtain the recovered data.
Besides, we also develop an analysis method for bit error rate prediction according to the different system parameters. By the analysis results, one can decide the system parameters depend on the design specifications instead of iterations.
Finally, we use Xilinx FPGA for function simulation of the recovery system. Moreover, a bit error measurement modules are built in to test the system performance. | en_US |