| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 邱瑞德 | zh_TW |
| DC.creator | Ran-De Cho | en_US |
| dc.date.accessioned | 2000-6-16T07:39:07Z | |
| dc.date.available | 2000-6-16T07:39:07Z | |
| dc.date.issued | 2000 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=87324011 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 其次我們提出一個新的全數位式時脈回復器的架構，並利用USB2的高速規格(480Mb/s)來驗證。USB2為一個新的電腦週邊萬用匯流排的規格，而USB2中的實體層製作主要包涵了接發端和時脈回復器，製作一個全數位式、低功率損耗和小面積時脈回復器是USB2中相當重要的一環。而我們除了提出這個時脈回復器之外，同時也提出了整個USB2實體層的製作架構。 | zh_TW |
| dc.description.abstract | Second, a clock recovery architecture and circuit is proposed for Universal Serial Bus 2 (USB2) high-speed mode (480M bits per second). USB2 is a new serial bus standard for the peripheral of PC today. The physical layer of USB2 consists of a transceiver and the clock recovery (CR). For USB2 high-speed 480M bits per second, it is important to design an all digital, low power, small area clock recovery. In this thesis, we propose an overall architecture of USB2 physical layer. We also propose a new all digital clock recovery for USB2 physical layer. However, it consume only when working at 480M bit per second. | en_US |
| DC.subject | 低雜訊 | zh_TW |
| DC.subject | 輸出緩衝器 | zh_TW |
| DC.subject | 時脈回復器 | zh_TW |
| DC.subject | 同時性邏輯轉換雜訊 | zh_TW |
| DC.subject | usb2 | en_US |
| DC.subject | output buffer | en_US |
| DC.subject | clock recovery | en_US |
| DC.subject | Simultaneous Switching Noise | en_US |
| DC.title | 低雜訊輸出緩衝器設計及USB2實體層的時脈回復器製作 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |