博碩士論文 87324013 完整後設資料紀錄

DC 欄位 語言
DC.contributor電機工程學系zh_TW
DC.creator呂誌忠zh_TW
DC.creatorChih-Chung Luen_US
dc.date.accessioned2000-7-11T07:39:07Z
dc.date.available2000-7-11T07:39:07Z
dc.date.issued2000
dc.identifier.urihttp://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=87324013
dc.contributor.department電機工程學系zh_TW
DC.description國立中央大學zh_TW
DC.descriptionNational Central Universityen_US
dc.description.abstractIn this thesis, a design methodology for Booth-encoded Montgomery’’s modular multiplication algorithms is proposed. The new design methodology helps us to re-duce the required iteration number in the Encryption/Decryption of RSA cryptosys-tem. With application of pipelining and folding/unfolding techniques to the design of Montgomery’’s modular multiplication module, we construct the processing element (PE) called M-cell. With the M-cell’’s, we can easily reconfigure the RSA chip. It is very convenient to reconfigure the RSA chip for different specification by cascade different number of M-cells and reuse them. The final optimized Montgomery’’s modular multiplication module is a digit-serial, pure-systolic, and scalable architec-ture with 100% utilization of all PE modules. The simulation result shows that we can not only reduce the required iteration number from 2n^2 to n^2 using H algorithm, hard-ware complexity is also simplified. The efficiency (time-area product) of our design is improved about a factor of 2.5. The simulation results show that the maximum speed-performance of single RSA chip can be up to 476kbit/sec.en_US
DC.subject密碼zh_TW
DC.subjectcryptographyen_US
DC.subjectcryptosystemen_US
DC.subjectRSAen_US
DC.subjectMontgomeryen_US
DC.subjectmodular multiplicationen_US
DC.subjectmodular exponentailen_US
DC.title適用於RSA公匙密碼系統之高效能Montgomery模組zh_TW
dc.language.isozh-TWzh-TW
DC.titleDesign Methodology of Booth-encoded Montgomery Module Design for RSA Cryptosystemen_US
DC.type博碩士論文zh_TW
DC.typethesisen_US
DC.publisherNational Central Universityen_US

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