| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 羅鋒 | zh_TW |
| DC.creator | Feng Lo | en_US |
| dc.date.accessioned | 2000-7-17T07:39:07Z | |
| dc.date.available | 2000-7-17T07:39:07Z | |
| dc.date.issued | 2000 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=87324017 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 第二代高速數位用戶迴路(HDSL2)被認為是使T1(1.544Mbps)服務更有經濟效率的解決方案。其最大的特點在於利用目前已架構的電話線用戶迴路即可提供T1服務，而且傳輸距離比既有的解決方案還遠。為達此目標，在HDSL2標準中，使用由脈衝振幅調變(PAM)及迴旋碼(convolutional code)所組成格子碼(TCM)為編碼標準。
在本論文中，我們實現了適用於HDSL2系統之迴旋碼編/解碼器。相較於編碼器，解碼器的電路複雜了許多，而且在實際硬體實現時，有許多要素需要列入考慮。在設計的過程中，我們針對實現維特比解碼器(Viterbi decoder)的要素加以探討，並且選定我們所要採用的架構；接著，我們以Matlab程式驗證整個編/解碼運作的過程，並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後，我們以Altera FLEX 10K200E來實現我們的設計。 | zh_TW |
| dc.description.abstract | In this thesis, we focus on the realization of the convolutional encoder/decoder. The hardware complexity of the decoder is much complicated than the encoder, and there are several implementation issues. In realization, we discuss the implementation issues and a proposed architecture is presented at first. Then, the encoding/decoding process is simulated Matlab program and verified by Verilog HDL. Finally, the encoder/decoder is realized by the FPGA device. | en_US |
| DC.subject | 第二代高速數位用戶迴路 | zh_TW |
| DC.subject | 迴旋碼 | zh_TW |
| DC.subject | 維等比解碼器 | zh_TW |
| DC.subject | 維等比演算法 | zh_TW |
| DC.subject | HDSL2 | en_US |
| DC.subject | concolutional code | en_US |
| DC.subject | Viterbi Decoder | en_US |
| DC.subject | Viterbi Algorithm | en_US |
| DC.title | 第二代高速數位用戶迴路中維特比解碼器之FPGA實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | FPGA Realization of the Viterbi Decoder for HDSL2 Systems | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |