| dc.description.abstract | Vector rotation plays an important role in many Digital Signal Processing (DSP) systems, such as discrete orthogonal transform, lattice-based digital filter, and direct digital frequency synthesizer. However, it is not a cost-efficient way to realize the vector rotation directly with multipliers and adders. Instead, a well-designed, cost-efficient, and high-performance vector rotator IP is necessary.
COordinate Rotational DIgital Computer (CORDIC) algorithm is a well-known technique to perform the rotational operation in digital arithmetic. After reviewing some CORDIC algorithms, we choose Extended Elementary Angle Set (EEAS) due to its characteristic of low-complexity, high precision, and high speed. Besides, pre-rotation scheme can help us improve the performance of EEAS-CORDIC in advanced.
In the part of implementing the key components, we make a discussion for delicate design issues, such as physical improvements and parameters arrangements. In order to cost down the hardware complexity, we use pass-nmos logic technique to implement barrel shifters. We develop mode selectors to control the operation mode, and save about 13% area for wiring in original design. Besides mode selectors provide the function for pre-rotation scheme without any other redundant hardware cost. In part of adder/subtractor design, we use the technique of carry save adder and carry look-ahead adder to improve the performance of our EEAS-CORDIC IP. Testing issues, however, are also considered in our design. In order to guarantee the quality of our EEAS-CORDIC IP, we use full custom design flow to optimize our design. The IP is fabricated in tsmc 0.35um 1P4M CMOS process, and the core area of EEAS-CORDIC with 16-bit precision is only 0.133 mm*mm. The post-simulation shows the IP can be operated at 150MHz of clock rate using 3V supply voltage. Compared with standard cell design, standard cell spend about 6 times of cost under the similar timing condition. | en_US |