| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 曾文亮 | zh_TW |
| DC.creator | Wenliang Tseng | en_US |
| dc.date.accessioned | 2006-10-12T07:39:07Z | |
| dc.date.available | 2006-10-12T07:39:07Z | |
| dc.date.issued | 2006 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=88541010 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文是論述連接線模型(interconnect models)應用在超大型積體電路系統的廣泛工作，其適用於探討連接線模型對於高速數位訊號的影響。對於基本模型，我們使用線邏輯(wired-logic)針對單晶片(SoC)系統提出一個有效率的連接線自我測試方法來解決驅動電路互斥的問題。並且測試信號可以重複使用，錯誤涵蓋率也可以提高，測試時間也同時被縮短。電腦的模擬驗證了數學分析與推導的正確性，也再次肯定此一方法的可行性。其次是quasi-TEM 模型，對於一般用途的被動性(passive)傳輸線巨集模型(macromodel)在高速電路模擬環境上的發展，我們提出兩個主題。第一個主題是為了解決分佈性傳輸線(distributed trans-mission lime)其階梯網路(ladder network)在模型簡化(model order reduction)前的準確度問題。基於這個問題，我們提出一個新的準則，能使階梯網路的分段數量最小化，並確認其準確性。為了應付這個問題，對於有限與無限分段數的階梯網路，其互導矩陣(admittance matrix) 需要以極點-殘值對 (pole-residue pairs)的方式呈現。然而，在運算的過程中，面臨高電腦運算量的挑戰。因此，我們提出精簡式子(compact closed forms)來縮短整個估算執行過程。並經由合理的例子來描述這個準則的可行性。另一個主題是對於混合型傳輸線與RLC元件網路系統其模型簡化問題。根據Krylov-subspace演算法，我們提出一個新的技術以求得簡化的巨集模型。經由使用DEPACT技術，將這個複雜的網路系統轉換成線性時間延遲系統(linear time-delay system)。其關鍵性是使用基底轉換式(unified formulation)來保持其簡化模型的被動性(passivity)。我們也利用數學的證明和模擬結果證實所提技術的合法性。再者這個技術可延伸到控制系統中解 模型簡化問題。由此，我們提出兩個定理來處理H-infinite範數有界(H-infinite norm bound)和被動性問題。根據定理，可藉由簡單線性矩陣不等式(linear matrix inequalities)的合適解(feasible solutions) 來得到簡化系統。因此，所提出的技術可提供一個有效率、準確和被動性的簡化系統應用在控制系統。 | zh_TW |
| dc.description.abstract | This thesis is a comprehensive works of interconnect models in VLSI system. The relative works are suitable to explore the influence of interconnect models on high-speed digital signal. For basic models, the wired-logic is used to propose an efficient interconnect BIST methodology to deal with the tri-state driver contention problem. It also improves the fault coverage and makes pattern reuse possible for SoC system. Simulation results verify the mathematical analysis and reassure the feasibility the methodology. For quasi-TEM models, two tasks focus on the development of the gen-eral-purpose passive transmission line macromodel for a circuit simulation environ-ment. The first task is in order to solve the accuracy problem of model order reduction for ladder networks of distributed transmission lines. Base on that, this work proposes a new criterion to be able to minimize the number of ladder sections to ensure the ac-curacy. The pole-residue pairs of admittance matrix for the finite and infinite sections of ladder networks are required to address the criterion. However, the challenge is numerical computation of CPU cost. Therefore, this work proposes compact closed forms to overcome the difficulty. The valid examples delineate the feasibility of the proposed criterion. The other task is model order reduction problem for mixed dis-tributed transmission line/RLC component network system. A novel technique based on Krylov-subspace algorithm is proposed to obtain reduced macromodel. The com-plex network can transform into a linear time-delay system using DEPACT technique. A key feature of the proposed technique is using a unified formulation to preserve passivity. The mathematical derivation proof and simulation results approve the vali-dation of the proposed technique. Moreover, this technique is also extended to solve the H-infinite model order reduction problem in control system. Two theorems are proposed to deal with H-infinite norm bound and passivity problems. Based on the theorems, the re-duced system is obtained from the feasible solutions of simple linear matrix inequali-ties. Therefore, the proposed technique provides an efficient, accurate and passive re-duced system to application in control system. | en_US |
| DC.subject | 自我建立測試 | zh_TW |
| DC.subject | 傳輸線 | zh_TW |
| DC.subject | 階梯網路 | zh_TW |
| DC.subject | 模型簡化 | zh_TW |
| DC.subject | 線性時間延遲系統 | zh_TW |
| DC.subject | Transmission Lines | en_US |
| DC.subject | Built-In Self Test | en_US |
| DC.subject | Ladder Networks | en_US |
| DC.subject | Model Order Reduction | en_US |
| DC.subject | Linear Time-delay System | en_US |
| DC.title | 超大型積體電路連結系統測試與分析 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Test and Analysis of VLSI Interconnect systems | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |