| dc.description.abstract | Due to process technologies scale-down, the operating frequency and circuit complexity of CMOS VLSI increase. The growing gap between on-chip gates and off-chip I/O bandwidth is reaching the critical proportions. Therefore, the interconnects between chips often limit the performance of a system in application such as network switches, routers, processor-memory interfaces, and multi-processor interconnection. For this reason, to integrate high speed serial links on chips can reduce the pin/wire count, and power budget of a system significantly.
There are two major topics in this thesis. First, we will focus on the study of channel modeling, signalling noise sources, binary versus modulation signalling, and low voltage differential signalling (LVDS) standard. Base on these considerations, we will propose the 2.5 Gbps transceiver that conforms to the LVDS specifications. Second, we will propose a transceiver architecture that uses proposed edge-position modulation (EPM), In contrast with pulse-amplitude modulation (PAM), EPM uses the pulse edge transition site in the transmitted symbol to denote digital codes. This transceiver for the physical layer of a serial link will have a data bandwidth of 5 Gbps. The circuit design and operational concept for the transmitter and receiver will be described.
In this thesis, a 2.5 Gbps transmitter has been implemented. It is compatible with the low voltage differential signalling (LVDS) standard. In a TSMC 0.25-μm CMOS technology, the transmitter circuit operates at 2.5 Gbps on a 2.5V power supply and occupies an area of 1.348*0.986mm2 . The technique to achieve 2.5 Gbps data rate is using point-to-point topology with serialization of data bits in transmitter and deserialization with tracking phase clock/data recovery techniques in receiver. | en_US |