| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 廖偉明 | zh_TW |
| DC.creator | Wei-Ming Liao | en_US |
| dc.date.accessioned | 2002-7-12T07:39:07Z | |
| dc.date.available | 2002-7-12T07:39:07Z | |
| dc.date.issued | 2002 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=89521035 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 本論文中，我們從設計到製作，研究深次微米Si/SiGe異質結構互補型電晶體元件在高頻與低功率消耗電路上的應用。在矽鍺應用於元件結構的設計上，我們利用二維解析軟體MEDICI 做以下幾個研究方向的結構模擬：首先，將矽鍺應用於MOS通道上，在relaxed Si1-yGey 材料上成長一strained Si1-xGex 層來當作p型電洞通道與一strained Si 層來當作n型電子通道，利用其高載子遷移率可以達到高速的要求；其次，分析矽鍺材料使用於源極與汲極之Si1-zGez S/D MOS結構，藉由異質接面能帶偏移而得以改善元件短通道效應降低功率消耗；最後發展一整合的互補型金氧半電晶體結構，使同時具有高速且低功率消耗的優點。我們除了模擬分析所設計結構的電性外，亦將探討模擬時各種機制對電性分析的影響。
我們實際製作矽鍺通道結構的p型矽/矽鍺異質結構電晶體並比較其通道鍺含量的影響，利用UHVCVD沈積三種濃度的矽鍺（鍺摻雜15％、30％、grading）當作電洞通道，並為了降低製程熱預算，避免矽鍺層應力變化，採用低壓化學氣相沉積法沉積TEOS閘極氧化層。最後利用電流-電壓等各式量測方法，探討元件之電性特性。 | zh_TW |
| dc.description.abstract | The traits of valence band offset and enhanced carrier mobility in SiGe/Si material system have attracted a lot of attention for high-speed device applications. In this study, a two-dimensional bandgap engineering technique was performed to design a high performance 0.1 um SiGe CMOSFET. A SiGe/Si heterostructure is proposed; in which strained SiGe layers are not only designed for p-channel but also included in source/drain to form heterojunction. And strained Si layer on SiGe layer is designed for nMOS. Simulation results showed that enhanced current-drive capability and reduced short channel effects are achievable within the proposed structure, which indicates that Si1-xGex/Si CMOSFET is a great benefit for high-speed and low-power CMOS circuit applications. And our experiment measurement result also shows the SiGe channel pMOS have better drive current and low substrate swing. | en_US |
| DC.subject | 矽鍺 | zh_TW |
| DC.subject | 互補型金氧半電晶體 | zh_TW |
| DC.subject | 高效能 | zh_TW |
| DC.subject | SiGe | en_US |
| DC.subject | CMOS | en_US |
| DC.subject | high performance | en_US |
| DC.title | 高效能矽鍺互補型電晶體之研製 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Design and Fabrication of high performance SiGe Complementary MOS Transistor | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |