| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 戴菁甫 | zh_TW |
| DC.creator | Jing-Fu Dai | en_US |
| dc.date.accessioned | 2004-6-29T07:39:07Z | |
| dc.date.available | 2004-6-29T07:39:07Z | |
| dc.date.issued | 2004 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=89541002 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 在積體電路的設計和發展上，半導體的數值模擬分析扮演一個非常重要的角色。但是在半導體元件的數值模擬過程中，往往需要解非常龐大的稀疏矩陣，所以在本論文中，將就半導體元件的模擬特性來改善階層化不完全LU分解法(Levelized Incomplete LU factorization)，並用來開發一個新的稀疏矩陣解法器。而為了提供半導體元件和混階電路模擬一個有效的發展環境，吾人將元件內部的物理特性轉化成等效電路的模式來方便程式的撰寫以及分析，吾人將描述載子傳輸的擴散模型藉由專業的技術加以分離，以轉換成一些等效電路元件，例如電壓控制電流源、電容等，但在利用傳統耦合模式(coupled method)的電路矩陣解法器將帕松和電流連續方程式轉換成等效電路的同時，由於彼此的交互影響而衍生出的相依電源(VCCS)將提高程式在維護和除錯上的困難度，因此，吾人提出利用分離模式(decoupled method)和部份分離模式(partial decoupled method)來簡化等效電路的模型，將帕松方程式、電洞和電子連續方程式分開處理，進而有效節省記憶體的空間運用並提升程式數值運算的收斂性。另外，在本論文中，吾人運用高效率之變數排列及分數型截斷參數之技巧進一步節省記憶體空間之運用，並藉由分散型態之非零生成項之組合方式有效提升程式數值運算之效能，繼而提出一套高性能的連結介面藉以妥善安置及收集分散的初始非零項來有效提升階層化不完全LU分解法之效率，並且這套介面能自動串聯所被模擬之電路或等效電路模型之各節點互相連結之資訊。因此，結合低記憶體需求、數值運算效能提升及連結介面的高效率將使階層化不完全LU分解法被廣泛的運用在任意結構之半導體元件或混階電路之模擬應用。 | zh_TW |
| dc.description.abstract | Numerical simulation of semiconductor devices plays a very important role in the design and development of integrated circuits. We will present a new circuit simulator with an improved Levelized Incomplete LU method to perform such simulations. To have an environment for evaluating the interaction between a semiconductor device and a circuit, we use the equivalent circuit approach. This approach allows for simple representation on the carrier transport models of devices through equivalent circuit elements such as voltage controlled current sources and capacitors. Next, we will present more efficient equivalent circuit model for decoupled method (DM) and partial decoupled method (PDM) in semiconductor device simulation. The effectiveness of the new methods exhibit a good stability and convergence rate, and user interaction with the computational process is significantly reduced. Low memory requirements and high efficiency should pave the two methods to its widespread application in multidimensional mixed-level semiconductor device and circuit simulation. Further, we present the high efficiency variable permutation method, interleaving method, and the fractional truncation parameter is used to save further memory consumption, and the distributed pattern makes a speed-up in the numerical iteration. Also, in order to effectively arrange and record the scattered nonzero items of sparse matrix A, we create a connection-table to raise the efficiency of L-ILU factorization. It will contain the information automatically about the interconnection of the simulated network or equivalent circuit model. | en_US |
| DC.subject | 階層化不完全LU分解 | zh_TW |
| DC.subject | 截斷參數 | zh_TW |
| DC.subject | 混階電路 | zh_TW |
| DC.subject | L-ILU factorization | en_US |
| DC.subject | truncation parameter | en_US |
| DC.subject | mixed-level circuit | en_US |
| DC.title | 含改良型L-ILU解法器及PDM電路表述之二維及三維元件數值模擬器之開發 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Development of 2-D and 3-D numerical device simulator includingan improved L-ILU solver and the circuit representation of PDM | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |