| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 林志憲 | zh_TW |
| DC.creator | Chih-Hsien Lin | en_US |
| dc.date.accessioned | 2006-6-15T07:39:07Z | |
| dc.date.available | 2006-6-15T07:39:07Z | |
| dc.date.issued | 2006 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=89541008 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 由於多媒體應用的增加，使得傳輸資料頻寬的需要量增大。 如果把高速串列連結傳輸應用在價格低廉的纜線上，將是非常節省成本的方法。 本論文中內完成適用於纜線的5-10Gbps傳收器之核心設計、規格建立及晶片製作。 目前傳收系統的核心主要是在傳輸端的編碼方式、傳輸收發電路的濾波器(Pre-emphasis or Equalizer)以及接收端的時序回復電路。 因為高速傳輸的應用，傳導纜線的頻率響應為一低通濾波的形式，且隨著纜線長度的增加，信號在高頻部份的衰減也會呈線性的增加。 因此在本論文中提出傳輸器信號預先增強器並分析其訊號在時域及頻域上的響應及現象。 在電路上則使用了自訂的預先加強之係數使得接收端電壓維持固定，其規格為300mV 10/5 Gbps(4/2 PAM)。
接著在此論文中提出一個全數位式時脈資料回復器電路設計，其架構相當的規律且是適用於不同的架構。 在TSMC .25製程下，其verilog程式合成結果之速度可達到5Gbps。由於我們用超取樣之方式實現全數位之資料回復電路架構，此論文亦分析一些重要的效能及設計參數並推導其分式使不同的設計參數可以符合不同的系統規格。 此外本論文亦對整個資料回復電路做一套影響系統效能的雜訊以及錯誤率分析並將影響系統效能的因素參數化。 | zh_TW |
| dc.description.abstract | Due to the increasing applications of multimedia in recent years, the requirement of data bandwidth has been increased. High speed serial link that achieves Gbps has the advantage of low cost and thus become popular. In this thesis, we achieve 5-10 Gbps transceiver system including core design, specification decision and IC implementation for cable transmission. The main structures of the transceiver system are transmission data encoder, and transmitter pre-emphasis, equalizer and clock recovery circuit of the receiver. Because of the application for the high speed data rate transmission, the cable exhibits like a low pass filter. Signal amplitude decreases when data rate increases. A transmitter with pre-emphasis is proposed. The time domain and frequency domain response analysis are carried out to show the performance. It uses custom coefficients of pre-emphasis to fix the signal amplitude in receiver node which is about 300mV for 10/5 Gbps (4/2 PAM).
In the thesis, we also proposed an all digital data clock recovery circuit which is very regular and flexible for different applications. We adopt an oversampling phase-picking method to realize an all digital data recovery circuit. Several key performance and design parameters are analyzed and formulated, therefore, different specifications can be met with different design parameters. Finally, we derive a set of jitter and BER analysis equations of the oversampling method. Using TSMC .25 CMOS process, this circuit can archive 5Gbps. | en_US |
| DC.subject | 預先增強器 | zh_TW |
| DC.subject | 串列連結 | zh_TW |
| DC.subject | 超取樣 | zh_TW |
| DC.subject | Pre-emphasis | en_US |
| DC.subject | Serial Link | en_US |
| DC.subject | Oversampling | en_US |
| DC.title | 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Multi-Gbps Serial Link Transmitter with Pre-emphasis and All Digital Data Recovery with Oversampling Method | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |