| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 趙明達 | zh_TW |
| DC.creator | Ming-Ta Chao | en_US |
| dc.date.accessioned | 2003-6-20T07:39:07Z | |
| dc.date.available | 2003-6-20T07:39:07Z | |
| dc.date.issued | 2003 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=90521035 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 中文摘要
本篇論文一開始主要是討論在二維的半導體元件模擬器中開發出一套向量繪圖(vector-plot)的方法。此向量繪圖的技術能提供我們去了解半導體元件內部的電流及電場的分佈情形。透過所畫出的箭頭, 我們可以很清楚的表示出電流及電場的大小和方向。其次，我們將提出一些模型(model)去探討金氧半電晶體(MOSFET)內部的非理想情況, 在本論文內所討論的非理想狀況包含場相關的遷移率(field-dependent mobility)，氧化層內的固定電荷(fixed charge in the oxide layer)。最後我們提出一個元素切割方法(element-cut method)去模擬BJT元件。元素切割方法中的二分切線(bisection lines)能夠幫助我們去計算BJT元件內部的電流分量。透過此元素切割方法，我們能解釋內部(internal) BJT的電流增益(current gain)大於合併(combined) BJT的電流增益之原因。 | zh_TW |
| dc.description.abstract | ABSTRACT
In this thesis, first we develop a vector-plot tool for 2-D device simulator. The vector-plot development technique can provide us to understand the distribution of the current flow and electric field inside the device. By the plot of the arrow, it is clear to show the magnitude and the direction of the current flow and electric field. Secondly, we will propose the model to discuss the nonideal cases of the MOSFET device. The nonideal cases are field-dependent mobility, fixed charge in the oxide layer in this thesis. Finally, we propose the element-cut method in the BJT device simulation. The bisection lines of the element-cut method can help us to calculate the current component inside the BJT device. We can explain that the current gain of the internal BJT is larger than the combined BJT by the element-cut method. | en_US |
| DC.subject | 半導體元件模擬電流和電場分析 | zh_TW |
| DC.subject | current-flow and electric-field analysis | en_US |
| DC.title | 二維半導體元件模擬的電流和電場分析 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | Current-flow and Electric-field Analysis in 2-D Semiconductor Device Simulation | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |