| DC 欄位 |
值 |
語言 |
| DC.contributor | 電機工程學系 | zh_TW |
| DC.creator | 程文聖 | zh_TW |
| DC.creator | Wen-Sheng Cheng | en_US |
| dc.date.accessioned | 2003-7-16T07:39:07Z | |
| dc.date.available | 2003-7-16T07:39:07Z | |
| dc.date.issued | 2003 | |
| dc.identifier.uri | http://ir.lib.ncu.edu.tw:88/thesis/view_etd.asp?URN=90521051 | |
| dc.contributor.department | 電機工程學系 | zh_TW |
| DC.description | 國立中央大學 | zh_TW |
| DC.description | National Central University | en_US |
| dc.description.abstract | 離散多頻（DMT）調變/解調方法是非對稱數位用戶迴路（ADSL）系統中標準的實體層傳輸技術。在離散多頻的傳收機中，通道的等化是經由兩個步驟所完成的，稱為時域等化器（TEQ）及頻域等化器（FEQ）。時域等化器的目的是用來縮短通道響應長度。而頻域等化器則是被用來補償信號經過通道時所造成的大小及相位的失真。
在本論文中，我們利用MATLAB完整的模擬此演算法並驗證其正確性。模擬的結果顯示TEQ-based ADSL接收器可以有效的將通道響應縮短，並且在頻率軸成功的把傳送的QAM 符號還原，我們利用SNR，SSNR，GSNR以及傳輸速率來評估其效能。
另一方面，在資料通路設計(datapath)上，我們針對通訊系統實際應用上不同運算需要，設計了不同種類的乘法累加器，包括single-MAC, dual-MAC,以及subword-MAC，我們提出了可參數化數位訊號處理器設計方法論，包括乘法器的位元長度以及保護字元，並且利用硬體描述語言Verilog完成了一系列針對通訊系統設計的可參數化資料通路設計。 | zh_TW |
| dc.description.abstract | Discrete multiton (DMT) modulation/demodulation scheme is the standard physical-layer transmission technology in ADSL system. In DMT transceiver, channel equalization is carried out through time domain equalizer (TEQ) and frequency domain equalizer (FEQ). TEQ is introduced to shorten the channel response to a pre-defined length. On the contrary, FEQ is used to compensate the magnitude and phase distortion caused by channel.
In this thesis, we use MATLAB to simulate the whole TEQ-FEQ algorithm and verify the correctness of this algorithm. The simulation results show that TEQ-based ADSL transceiver shorten the channel impulse response effectively, and recover the transmitted QAM-symbol in frequency domain. We evaluate the performance of this algorithm by SNR, SSNR, GSNR, and data rate.
On the other hand, we design different kinds of MAC for communication system requirements, include single-MAC, dual-MAC, and subword-MAC. We propose the parameterized DSP processor design methodology, and the word length and guard bit in MAC are be parameterized. We implement the parameterized DSP data path by hardware description language-Verilog. | en_US |
| DC.subject | 非對稱性數位用戶迴路 | zh_TW |
| DC.subject |
FEQ | en_US |
| DC.subject | TEQ | en_US |
| DC.subject | DMT | en_US |
| DC.subject | DSP | en_US |
| DC.subject | ADSL | en_US |
| DC.title | 非對稱性數位用戶迴路之等化器系統及數位訊號處理器實現 | zh_TW |
| dc.language.iso | zh-TW | zh-TW |
| DC.title | A DSP Processor Approach for ADSL Equalization System | en_US |
| DC.type | 博碩士論文 | zh_TW |
| DC.type | thesis | en_US |
| DC.publisher | National Central University | en_US |