| dc.description.abstract | The project of this thesis is analog front-end circuits design for IF receiver. It concludes two components – an automatic gain control system design and an analog-to-digital system design.
In the automatic gain control system design, this system is a feedback closed loop control system and its gain can be controlled by this feedback closed loop system. Because of this gain control mechanism, the output of the system has constant magnitude with different input magnitude swings, and the output signal will have lower distortion. When input signal is 100MHz, the gain control range of this system is 30dB and the input signal range is from 10mVpp to 300mVpp. The technology is UMC018 process, power supply is 1.8V, and power consumption is 21mW.
In the analog-to-digital converter system design, a 100MSs/s 10-bit pipelined analog-to-digital converter system is designed, and it will used in the cable modem communication system or HDTV. This converter utilizes pipelined architecture to have 100MS/s conversion rate. In sample-and-hold amplifier design, it utilizes the flip-around architecture to have best feedback closed loop factor, so the OP in the sample-and-hold amplifier will cost lower power. The coarse quantizer can tolerate 500mV comparator offset without overflow by digital error correction technique. The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The technology is TSMC018 process 3.3V CMOS model, power supply is 3.3V, and power consumption is 557mW. | en_US |