| dc.description.abstract | In this thesis, we not only propose a set of jitter analysis but also discuss the technique of the odd and even oversampling ratio. First the estimation formulas are obtained by dividing jitter into two types, random and deterministic jitter. Then we modify them to match the actually characteristics of circuits. In designing circuits, the odd oversampling ratio will cause area waste when the ratio is from one to another such as 3x to 5x. Therefore, we discuss the even oversampling ratio in this thesis.
Besides, for verifying the reliability of derived formulas, we also propose a method to check them. Here, we need to do two things before simulation. First thing is to create the transmitted bit pattern with jitter. Second thing is to create synthesizable RTL code from module generator. Then we use design analyzer of synopsys to generate gate level circuits. Finally, the simulation can be done by combining bit pattern with jitter and gate level circuits.
In the development of module generator, overall circuits are parameterized for making design more flexible. Besides, our user interface is based on C language. The verilog code will be generated automatically by users, who input the systematic parameters step by step through the user interface. Due to the regular circuit design, it is easy to implement by cell-based design flow. Therefore, it is very suitable to be a soft silicon intellectual property. Finally, a design example generated by the module generator is implemented in a cell-based design method using the TSMC 0.25um 1P5M cell library. Without preamble circuit, the maximum performance of the design, which the oversampling ratio is given 3, sliding windows is given 3 and the number of bits in a sliding window is given 8, can reach 2.5Gbps. The maximum performance of the design can reach 2.5Gbps and the other examples with various specifications are also listed in Chapter 6. | en_US |